Digital coarse locking in digital phase-locked loops

A digital phase-locked loop (DPLL) circuit comprising:

• a coarse time-to-digital converter (TDC) and a coarse digital loop filter (DLF) that are configured to be coupled between a reference clock source and a digitally controlled oscillator (DCO), wherein the coarse TDC comprises:
• a first edge detection circuit configured to detect a first edge of a reference clock signal from the reference clock source;
• a second edge detection circuit configured to detect a second edge of a first clock signal, wherein the first clock signal is based on an output of the DCO divided by a dividing factor, wherein the second edge comprises a closest edge to the first edge;
• a counter configured to count the number of clock cycles of a second clock signal, wherein the second clock signal is the output of the DCO divided by a fixed dividing factor;
• a first register configured to latch a first output value of the counter at the first edge of the reference clock signal;
• a second register configured to latch a second output value of the counter at the second edge of the first clock signal;
• a subtractor circuit configured to compute a first difference between the second output value and the first output value of the counter, and
• a saturation circuit configured to detect cycle slipping between the reference clock signal and the first clock signal and configured to saturate the first difference to a pre-determined value when cycle slipping is detected;
• a first frequency divider circuit coupled to the DCO, wherein the first frequency divider circuit is configured to generate the first clock signal by dividing the output of the DCO by the dividing factor;
• and
• a second frequency divider circuit coupled between the DCO and the coarse TDC, wherein the second frequency divider circuit is configured to generate the second clock signal by dividing the output of the DCO by the fixed dividing factor.

A digital phase-locked loop (DPLL) circuit comprising:

• a coarse time-to-digital converter (TDC) and a coarse digital loop filter (DLF) that are configured to be coupled between a reference clock source and a digitally controlled oscillator (DCO), wherein the coarse TDC is configured to, during an acquisition mode of the DPLL circuit, generate a phase error by:
• receiving a reference clock signal from the reference clock source;
• receiving a first clock signal that is based on an output of the DCO divided by a dividing factor;
• computing a phase error using the reference clock signal and the first clock signal;
• comparing a magnitude of the phase error with a threshold value;
• and
• in response to detecting that the magnitude of the phase error is equal to or larger than the threshold value, saturating the magnitude of the computed phase error to the threshold value;
• and
• a first frequency divider circuit coupled to the DCO, wherein the first frequency divider circuit is configured to generate the first clock signal by dividing the output of the DCO by the dividing factor.