Delay-locked loop offset calibration and correction
AssigneeAdvanced Micro Devices, Inc.
InventorsAndy Huei Chu, Karthik Gopalakrishnan, Pradeep Jayaraman
Life of this patent
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Abstract
A clocking circuit is provided using a master delay-locked loop (DLL) and a slave DLL. A master DLL code indicates a delay adjustment made at a master DLL. A delay of a slave DLL is adjusted based on the master DLL code. A replica phase detector at the slave DLL is temporarily enabled during an interface idle period. A slave DLL code is determined, and a configuration value is determined based on the slave DLL code to the master DLL code. The replica phase detector is then disabled.
Claims20
A method for operating an interface circuit, comprising:
- providing a master delay-locked loop (DLL) lock value indicating a delay adjustment made at a master DLL;
- adjusting a delay of a slave DLL based on a master DLL code;
- and
- temporarily enabling a replica phase detector at the slave DLL during an interface idle period, determining a slave DLL code, determining a configuration value based on the slave DLL code to the master DLL code, and then disabling the replica phase detector.
A clocking circuit for a communication link comprising:
- a master delay-locked loop (DLL) circuit comprising a plurality of delay elements and a phase detector circuit for detecting a phase offset and providing a master DLL code for adjusting the delay elements of the master DLL;
- a slave DLL circuit for providing an oscillator signal to a receiver of the communication link, the slave DLL circuit comprising a plurality of delay elements and a replica phase detector circuit for detecting a phase offset and providing a slave DLL code for adjusting the delay elements of the slave DLL circuit;
- and
- an arbiter circuit operable to temporarily enable the replica phase detector circuit of the slave DLL circuit during an idle period of the communication link to update a configuration value based on the master DLL code and the slave DLL code.
A data processing system, comprising:
- a data processor;
- a memory coupled to the data processor by a communication link;
- and
- a clocking circuit for the communication link comprising:
- a master delay-locked loop (DLL) circuit comprising a plurality of delay elements, and a phase detector circuit for detecting a phase offset and providing a master DLL code for adjusting the delay elements of the master DLL;
- a slave DLL circuit for providing an oscillator signal to a receiver of the communication link, the slave DLL circuit comprising a plurality of delay elements, and a replica phase detector circuit for detecting a phase offset and providing a slave DLL code for adjusting the delay elements of the slave DLL circuit;
- and
- an arbiter circuit operable to temporarily enable the replica phase detector circuit of the slave DLL circuit during an idle period of the communication link to update a configuration value based on the master DLL code and the slave DLL code.
Dependencies are inferred from the claim text.