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US 11,909,403 B2Granted
Low power apparatus and method to multiply frequency of a clock
AssigneeIntel Corporation
InventorsKuan-Yueh Shen, Nasser Kurd
Life of this patent
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Abstract
A multi-feedback circuit that compares a duty cycle corrected reference clock fREF, and controls a number of identical delay lines to generate a new clock with a frequency that is a multiple (e.g., 32×, 4×, etc.) of the frequency of fREF with approximately 50% duty cycle (DC). The new clock is used as a reference clock to a phase locked loop (PLL) or a multiplying delay locked loop (MDLL) resulting in shorter lock times for the PLL/MDLL, higher bandwidth for the PLL/MDLL, lower long-term output clock jitter. The multi-feedback circuit can also be used as a low power clock generator.
Claims15
An apparatus comprising:
- a duty cycle correction (DCC) circuit to receive a first clock having a first frequency to generate an output which is substantially corrected for duty cycle error;
- and
- a multiplier circuitry coupled to the output of the DCC circuit, wherein the multiplier circuitry is to generate a second clock having a second frequency higher than the first frequency, wherein the multiplier circuitry includes:
- a delay line to delay the output of the DCC circuit, and to generate a phase shifted signal;
- and
- a comparator to compare the output of the DCC circuit and the phase shifted signal wherein the delay line is a first delay line, the phase shifted signal is a first phase shifted signal, and the multiplier circuitry comprises a second delay line to delay the first phase shifted signal and generate a second phase shifted signal, an inverter to invert the second phase shifted signal, and a phase detector to receive an output of the inverter, and the output of the DCC circuit.
3 more elements
An apparatus comprising:
- a duty cycle correction (DCC) circuit to receive a first clock having a first frequency to generate an output which is corrected for duty cycle error;
- and
- a multiplier circuitry coupled to the output of the DCC circuit, wherein the multiplier circuitry is to generate a second clock having a second frequency higher than the first frequency, wherein the multiplier circuitry is independent of a phase locked loop, and wherein the multiplier circuitry includes:
- a first delay line to delay the output of the DCC circuit and generate a substantially 90 degree phase shifted signal,
- an XOR gate to compare the output of the DCC circuit and the substantially 90 degree phase shifted signal,
- a second delay line to delay the substantially 90 degree phase shifted signal and generate a substantially 180 degree phase shifted signal,
- an inverter to invert the substantially 180 degree phase shifted signal;
- and
- a phase frequency detector to receive an output of the inverter, and the output of the DCC circuit.
6 more elements
A system comprising:
- a crystal oscillator to generate a first clock having a first frequency;
- a memory;
- a processor coupled to the memory;
- and
- a wireless interface to allow the processor to communicate with another device, wherein the processor includes:
- a duty cycle correction (DCC) circuit to receive the first clock to generate an output which is corrected for duty cycle error;
- and
- a multiplier circuitry coupled to the output of the DCC circuit, wherein the multiplier circuitry is to generate a second clock having a second frequency higher than the first frequency, wherein the multiplier circuitry includes:
- a delay line to delay the output of the DCC circuit, and to generate a phase shifted signal;
- and
- a comparator to compare the output of the DCC circuit and the phase shifted signal, wherein the delay line is a first delay line, the phase shifted signal is a first phase shifted signal, and the multiplier circuitry comprises a second delay line to delay the first phase shifted signal and generate a second phase shifted signal, an inverter to invert the second phase shifted signal, and a phase detector to receive an output of the inverter, and the output of the DCC circuit.
8 more elements
Dependencies are inferred from the claim text.