System and semiconductor device therein

A method, comprising:

• delaying, by a delaying circuit, a first enable signal by a first delay time period to generate a second enable signal;
• generating, by a detecting circuit, a feedback signal according to a voltage level of a first clock signal at a moment of an edge of the second enable signal;
• and
• adjusting, by a controlling circuit, the first delay time period according to the feedback signal, until the edge of the second enable signal is aligned with an edge of the first clock signal.

A device, comprising:

• a dividing circuit configured to divide a first clock signal to generate a first enable signal;
• a delaying circuit configured to delay the first enable signal according to a feedback signal, to generate a second enable signal;
• a gating circuit configured to receive the second enable signal and be triggered by the first clock signal;
• and
• a detecting circuit configured to receive the first clock signal and be triggered by the second enable signal, to generate the feedback signal.