Integrated circuit including back side conductive lines for clock signals
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKam-Tou Sio, Jiun-Wei Lu
Life of this patent
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Abstract
An integrated circuit is provided, including a first latch circuit, a second latch circuit, and a clock circuit. The first latch circuit transmits multiple data signals to the second latch circuit through multiple first conductive lines disposed on a front side of the integrated circuit. The clock circuit transmits a first clock signal and a second clock signal to the first latch circuit and the second latch circuit through multiple second conductive lines disposed on a backside, opposite of the front side, of the integrated circuit.
Claims20
An integrated circuit, comprising:
- a flip flop circuit configured to operate in response to a plurality of data signals transmitted through a plurality of first conductive lines disposed on a front side of the integrated circuit and a first clock signal and a second clock signal that are received from a plurality of second conductive lines disposed on a back side, opposite of the front side, of the integrated circuit, and comprising:
- a first inverter configured to generate the first clock signal in response to a third clock signal received from a third conductive line on the front side;
- and
- a second inverter configured to generate the second clock signal in response to the first clock signal transmitted by a first line in the plurality of second conductive lines.
An integrated circuit, comprising:
- a first transistor comprising a first gate and a first active region, and configured to output a first clock signal at the first active region in response to a second clock signal received at the first gate through a first conductive line in a first layer on a back side of the integrated circuit;
- and
- a first latch circuit comprising a second transistor that comprises a second gate and is configured to output, in response to the first clock signal received at the second gate through a second conductive line in the first layer on the back side, a signal to a data out circuit through a third conductive line in a first layer on a front side, opposite the back side, of the integrated circuit.
A method, comprising:
- forming a plurality of first conductive lines in a first layer on a back side of an integrated circuit to transmit a first clock signal and a second clock signal inverted from the first clock signal;
- forming a plurality of second conductive lines in a second layer, below the first layer, on the back side of the integrated circuit to transmit the first clock signal and the second clock signal between the plurality of first conductive lines, wherein the first layer is disposed between the second layer on the back side and a front side of the integrated circuit;
- and
- forming a plurality of third conductive lines extending parallel to the plurality of second conductive lines in the second layer on the back side of the integrated circuit to transmit a first supply voltage, wherein the plurality of first conductive lines and the plurality of second conductive lines are interposed between the plurality of third conductive lines.
Dependencies are inferred from the claim text.