Level shifter circuit

A level shifter circuit, comprising:

• a first input terminal and a second input terminal, wherein each of the first input terminal and the second input terminal is configured to receive an input signal having a level between a first potential level and a first reference potential level;
• a first output terminal and a second output terminal, wherein each of the first output terminal and the second output terminal is configured to output an output signal having a level between a second potential level higher than the first potential level and a second reference potential level;
• a second potential supply node configured to supply a voltage at the second potential level;
• a first reference potential supply node configured to supply a voltage at the second reference potential level;
• a second reference potential supply node;
• a third reference potential supply node;
• a first direct current power supply;
• a second direct current power supply;
• a first resistance element;
• a second resistance element;
• a first impedance element and a second impedance element;
• a first transistor having a first conductivity type;
• a second transistor having a second conductivity type;
• a third transistor having the first conductivity type;
• a fourth transistor having the second conductivity type;
• and
• a first node and a second node, wherein
• a control terminal of the second transistor is connected to the first input terminal,
• a control terminal of the fourth transistor is connected to the second input terminal,
• the first node is connected to the first output terminal,
• the second node is connected to the second output terminal,
• the first transistor is connected between the second potential supply node and the first node,
• the second transistor is connected between the first reference potential supply node and the first node,
• the third transistor is connected between the second potential supply node and the second node,
• the fourth transistor is connected between the first reference potential supply node and the second node,
• each of the first impedance element and the second impedance element includes at least three terminals and at least one capacitance element,
• a first terminal of the first impedance element is connected to the control terminal of the second transistor,
• a second terminal of the first impedance element is connected to the second node,
• a third terminal of the first impedance element is connected to a control terminal of the first transistor,
• a first terminal of the second impedance element is connected to the control terminal of the fourth transistor,
• a second terminal of the second impedance element is connected to the first node,
• a third terminal of the second impedance element is connected to a control terminal of the third transistor,
• the first direct current power supply and the first resistance element are connected in series in this order from a side of the second reference potential supply node,
• the first direct current power supply and the first resistance element are between the second reference potential supply node and the control terminal of the first transistor,
• the third terminal of the first impedance element is connected between the first resistance element and the control terminal of the first transistor,
• the second direct current power supply and the second resistance element are connected in series in this order from a side of the third reference potential supply node,
• the second direct current power supply and the second resistance element are between the third reference potential supply node and the control terminal of the third transistor, and
• the third terminal of the second impedance element is connected between the second resistance element and the control terminal of the third transistor.