Direct-drive D-mode GaN half-bridge power module

A power semiconductor switching device comprising:

• a high-side switch and a low-side switch connected in series in a half-bridge configuration, between a high voltage DC bus and a low voltage DC bus, the high side switch being connected to the low side switch at a switching node, wherein:
• the high-side switch is a normally-off switch wherein a first normally-on GaN transistor switch (Q1) is connected in series with a normally-off Si MOSFET switch (M1), the source of Q1 being connected to the drain of M1;
• the low side switch is a normally-on switch, comprising a second normally-on GaN transistor switch (Q2);
• wherein gates of the D-mode normally-on GaN transistor switches Q1 or Q2 are directly driven, and the gate of the E-mode normally-off Si MOSFET M1 is directly driven by a control circuit, wherein M1 acts as a protection FET to hold the high-side switch in an off-state during start-up and during a fault condition;
• and
• the control circuit is configured to determine an operational mode of M1 responsive to an undervoltage lock-out (UVLO) signal and a voltage sense signal indicative of an overcurrent event, the control circuit operating so that:
• M1 is OFF during start-up until UVLO is off;
• M1 is ON for normal operation;
• M1 is turned-off during a fault condition if UVLO is turned-on;
• and if overcurrent protection (OCP) is triggered, M1 is ON and Q1 and Q2 are turned-off.

A power semiconductor switching device comprising:

• a high-side switch and a low-side switch connected in series in a half-bridge configuration, between a high voltage DC bus and a low voltage DC bus, the high side switch being connected to the low side switch at a switching node, wherein
• the high-side switch is a normally-off switch wherein a first normally-on GaN transistor switch (Q1) is connected in series with a normally-off Si MOSFET switch (M1), the source of Q1 being connected to the drain of M1;
• the low side switch is a normally-on switch, comprising a second normally-on GaN transitory switch (Q2);
• and
• Q1 has a source, a drain and a gate, wherein the drain of Q1 is connected to the high voltage DC bus and the source of Q1 is connected to a drain of M1, and the gate of Q1 is connected to a first gate drive terminal for directly driving the gate of Q1;
• the source of M1 is connected to the switching node, a gate of M1 is connected to an enable (control) terminal for directly driving the gate of the M1;
• a high-side ground terminal is connected to the source of M1;
• and a voltage sense terminal is connected to a common point between the source of Q1 and the drain of M1;
• and
• Q2 has a source, a drain and a gate, the drain of Q2 is connected to the switching node and the source of Q2 is connected to the low voltage DC bus, and the gate of Q2 is connected to a second gate drive terminal for directly driving the gate of Q2;
• and a low-side ground terminal is connected to the source of Q2.

A power semiconductor switching device comprising:

• a high-side switch and a low-side switch connected in series in a half-bridge configuration, between a high voltage DC bus and a low voltage DC bus, the high side switch being connected to the low side switch at a switching node, wherein:
• the high-side switch is a normally-off switch wherein a first normally-on GaN transistor switch (Q1) is connected in series with a normally-off Si MOSFET switch (M1), the source of Q1 being connected to the drain of M1;
• and
• the low side switch is a normally-on switch, comprising a second normally-on GaN transistor switch (Q2);
• and
• a half-bridge driver circuit comprising:
• a high-side driver for directly driving a gate of Q1;
• a low-side driver for directly driving a gate of Q2;
• wherein the high-side driver and the low-side driver are driven by PWM input signals INH and INL respectively;
• and
• a control circuit for driving M1, wherein the control circuit comprises a gate driver for providing an enable (control) signal for directly driving the gate of M1 in response to a gate input signal PGOOD,
• the control circuit having a voltage sense input Vsen from a voltage sense terminal connected to a node between the source of Q1 and the drain of M1,
• circuitry for receiving an undervoltage lock-out (UVLO) signal, and determining a power status and operational mode for M1,
• circuitry for comparing the voltage sense input Vsen to a reference overcurrent protection (OCP) limit voltage VOCP_limit, wherein said enable signal provides that
• M1 is OFF during start-up until UVLO is off;
• M1 is ON for normal operation;
• M1 is turned-off during a fault condition if UVLO is turned-on;
• and
• if OCP is triggered, M1 is ON and Q1 and Q2 are turned-off.