Memory devices including indium-containing materials, and related electronic systems

A memory device, comprising:

• a stack structure including tiers each comprising conductive material and insulative material vertically neighboring the conductive material, the stack structure having a memory array region and a staircase region horizontally neighboring the memory array region;
• strings of memory cells within a horizontal area of the memory array region and vertically extending through the stack structure;
• a staircase structure within a horizontal area of the staircase region and having steps comprising horizontal ends of at least some of the tiers of the stack structure;
• conductive contact structures in contact with the conductive material of the at least some of the tiers of the stack structure at the steps of the staircase structure;
• and
• vertical transistors vertically overlying the stack structure and within the horizontal area of the staircase region, at least one of vertical transistors comprising:
• indium-containing material having:
• a bottom section coupled to one of the conductive contact structures;
• a top section vertically overlying the bottom section;
• and
• a middle section vertically extending from and between the bottom section and the top section, the middle section having a lower atomic concentration of indium than each of the bottom section and the top section and comprising:
• a lower surface in physical contract with and substantially confined within a horizontal area of an upper surface of the lower section of the indium-containing material, the lower surface of the middle section of the indium-containing material having a smaller horizontal area than the horizontal area of the upper surface of the lower section of the indium-containing material;
• outer side surfaces in physical contract with dielectric material, the outer side surfaces comprising:
• a lowermost vertical boundary substantially coplanar with a lowermost vertical boundary of the dielectric material;
• and
• an uppermost vertical boundary substantially coplanar with an uppermost vertical boundary of the dielectric material;
• and
• inner side surfaces opposing the outer side surfaces and in physical contact with dielectric fill material having an upper surface vertically underlying the uppermost vertical boundary of the dielectric material, the inner side surfaces comprising:
• a lowermost vertical boundary vertically overlying the lowermost vertical boundary of the dielectric material;
• and
• an uppermost vertical boundary substantially coplanar with the uppermost vertical boundary of the dielectric material;
• conductive gate material horizontally neighboring and within vertical boundaries of the middle section of the indium-containing material;
• and
• the dielectric material, the dielectric material horizontally extending from and between the middle section of the indium-containing material and the conductive gate material.

A 3D NAND Flash memory device, comprising:

• a stack structure comprising conductive structures vertically alternating with insulative structures;
• pillar structures comprising semiconductive material extending through the stack structure;
• a staircase structure having steps partially defined by horizontal ends of at least some of the conductive structures of the stack structure;
• conductive contact structures in physical contact with the steps of the staircase structure;
• string driver transistors vertically overlying and horizontally overlapping the staircase structure, the string driver transistors individually comprising:
• a heterogeneous lower contact structure in physical contact with one of the conductive contact structures and including a first material comprising:
• a first atomic concentration of indium;
• and
• a first atomic concentration of oxygen;
• a channel structure in physical contact with the heterogeneous lower contact structure and including a second material comprising:
• a second atomic concentration of indium less than the first atomic concentration of indium;
• and
• a second atomic concentration of oxygen greater than the first atomic concentration of oxygen;
• a heterogeneous upper contact structure in physical contact with the channel structure and having a non-planar lower boundary, the heterogeneous upper contact structure including a third material comprising:
• a third atomic concentration of indium greater than the second atomic concentration of indium;
• and
• a third atomic concentration of oxygen less than the second atomic concentration of oxygen;
• gate dielectric material in physical contact with and substantially covering outer side surfaces of the channel structure, the channel structure and the gate dielectric material each substantially confined within a horizontal area of the heterogeneous lower contact structure;
• and
• gate electrode material in physical contact with and partially covering outer side surfaces of the gate dielectric material.

An electronic system, comprising:

• a processor device operably coupled to an input device and an output device;
• and
• a memory device operably coupled to the processor device and comprising:
• a stack structure including tiers each comprising conductive material and insulative material vertically neighboring the conductive material, the stack structure having a memory array region and a staircase region horizontally neighboring the memory array region;
• pillar structures comprising semiconductive material within horizontal boundaries of the memory array region and vertically extending through the stack structure;
• a staircase structure within horizontal boundaries of the staircase region and having steps comprising edges of at least some of the tiers of the stack structure;
• conductive contact structures on the steps of the staircase structure;
• and
• transistors vertically overlying the stack structure and within the horizontal boundaries of the staircase region, at least one of transistors comprising:
• a first indium-containing structure on one of the conductive contact structures;
• a second indium-containing structure over the first indium-containing structure;
• a third indium-containing structure vertically interposed between the first indium-containing structure and the second indium-containing structure, the third indium-containing structure having one or more of a lower atomic concentration of indium and a greater atomic concentration of oxygen than each of the first indium-containing structure and the second indium-containing structure;
• at least one gate electrode horizontally neighboring and within vertical boundaries of the third indium-containing structure;
• and
• gate dielectric material horizontally interposed between the third indium-containing structure and the at least one gate electrode, the gate dielectric material and the third indium-containing structure each substantially confined within a horizontal area of the first indium-containing structure.