US 11,908,929 B2Granted

Semiconductor device

AssigneeFuji Electric Co., Ltd.

InventorKeiji Okumura

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Abstract

A semiconductor device having an active portion and a gate pad portion on a semiconductor substrate includes: a first semiconductor layer of a first conductivity type; and a second semiconductor layer of a second conductivity type. The active portion has: first semiconductor regions of the first conductivity type; a first electrode provided on the first semiconductor regions; and first trenches. The gate pad portion has: a gate electrode pad provided above the second semiconductor layer; second trenches provided beneath the gate electrode pad; and second semiconductor regions of the second conductivity type, each provided in the first semiconductor layer so as to be in contact with a respective one of bottoms of the second trenches. Each of the second trenches is continuous with a respective one of the first trenches. The second semiconductor layer is continuous from the active portion to the gate pad portion.

Claims18

Dependent claims

A semiconductor device having an active portion and a gate pad portion on a semiconductor substrate, the semiconductor device comprising:

a first semiconductor layer of a first conductivity type, the first semiconductor layer having a first surface and a second surface opposite to each other;
a second semiconductor layer of a second conductivity type, provided on the first surface of the first semiconductor layer, the second semiconductor layer having a first surface and a second surface opposite to each other, the second surface of the second semiconductor layer facing the first semiconductor layer;
in the active portion:
a plurality of first semiconductor regions of the first conductivity type, selectively provided in the second semiconductor layer at the first surface thereof;
a first electrode provided on the first semiconductor regions;
and
a plurality of first trenches penetrating through the first semiconductor regions and the second semiconductor layer and reaching the first semiconductor layer, the first trenches extending in beneath the first electrode in an extending direction that is parallel to the first surface of the first semiconductor layer;
in the gate pad portion:
a gate electrode pad provided above the second semiconductor layer;
a plurality of second trenches provided beneath the gate electrode pad, the second trenches extending in the extending direction;
and
a plurality of second semiconductor regions of the second conductivity type, each provided in the first semiconductor layer so as to be in contact with a respective one of bottoms of the second trenches;
and
one or more third semiconductor regions of the second conductivity type, each of which is provided in the first semiconductor layer so as to be in contact with a corresponding one of two opposing sidewalls of the second trenches, and electrically connects the second semiconductor layer and a corresponding one of the second semiconductor regions, wherein
each of the second trenches is continuous with a respective one of the first trenches, and
the second semiconductor layer is continuous from the active portion to the gate pad portion.

13 more elements

A semiconductor device having an active portion and a gate pad portion on a semiconductor substrate, the semiconductor device comprising:

a first semiconductor layer of a first conductivity type, the first semiconductor layer having a first surface and a second surface opposite to each other;
a second semiconductor layer of a second conductivity type, provided on the first surface of the first semiconductor layer, the second semiconductor layer having a first surface and a second surface opposite to each other, the second surface of the second semiconductor layer facing the first semiconductor layer;
in the active portion:
a plurality of first semiconductor regions of the first conductivity type, selectively provided in the second semiconductor layer at the first surface thereof;
a first electrode provided on the first semiconductor regions;
and
a plurality of first trenches penetrating through the first semiconductor regions and the second semiconductor layer and reaching the first semiconductor layer, the first trenches extending in beneath the first electrode in an extending direction that is parallel to the first surface of the first semiconductor layer;
in the gate pad portion:
a gate electrode pad provided above the second semiconductor layer;
a plurality of second trenches provided beneath the gate electrode pad, the second trenches extending in the extending direction;
and
a plurality of second semiconductor regions of the second conductivity type, each provided in the first semiconductor layer so as to be in contact with a respective one of bottoms of the second trenches;
and
a plurality of fourth semiconductor regions of the second conductivity type, each of which is provided in the first semiconductor layer so as to be in contact with a respective one of bottoms of the first trenches, wherein
each of the second trenches is continuous with a respective one of the first trenches,
the second semiconductor layer is continuous from the active portion to the gate pad portion, and
each of the fourth semiconductor regions is continuous with a respective one of the second semiconductor regions.

14 more elements

A semiconductor device having an active portion and a gate pad portion on a semiconductor substrate, the semiconductor device comprising:

a first semiconductor layer of a first conductivity type, the first semiconductor layer having a first surface and a second surface opposite to each other;
a second semiconductor layer of a second conductivity type, provided on the first surface of the first semiconductor layer, the second semiconductor layer having a first surface and a second surface opposite to each other, the second surface of the second semiconductor layer facing the first semiconductor layer;
in the active portion:
a plurality of first semiconductor regions of the first conductivity type, selectively provided in the second semiconductor layer at the first surface thereof;
a first electrode provided on the first semiconductor regions;
and
a plurality of first trenches penetrating through the first semiconductor regions and the second semiconductor layer and reaching the first semiconductor layer, the first trenches extending in beneath the first electrode in an extending direction that is parallel to the first surface of the first semiconductor layer;
in the gate pad portion:
a gate electrode pad provided above the second semiconductor layer;
a plurality of second trenches provided beneath the gate electrode pad, the second trenches extending in the extending direction;
and
a plurality of second semiconductor regions of the second conductivity type, each provided in the first semiconductor layer so as to be in contact with a respective one of bottoms of the second trenches;
a plurality of fourth semiconductor regions of the second conductivity type, each of which is provided in the first semiconductor layer so as to be in contact with a respective one of bottoms of the first trenches;
and
one or more fifth semiconductor regions of the second conductivity type, each of which is provided in the first semiconductor layer so as to be in contact with a corresponding one of two opposing sidewalls of the first trenches, and electrically connects the second semiconductor layer and a corresponding one of the fourth semiconductor regions, wherein
each of the second trenches is continuous with a respective one of the first trenches, and
the second semiconductor layer is continuous from the active portion to the gate pad portion.

14 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/974,130Filed 26 Oct 2022 · continuation
Priority: JP 2020-11096326 Jun 2020
Published: US 2023/0049039 A116 Feb 2023
Granted: 20 Feb 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10D 30/668
Vertical dmos [vdmos] fets: having trench gate electrodes, e.g. UMOS transistors
H10D 30/0297
Of vertical dmos [vdmos] fets: using recessing of the gate electrodes, e.g. to form trench gate electrodes
H10D 62/107
Having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or…:…
H10D 62/8325
Being Group IV materials comprising two or more elements, e.g. SiGe: silicon carbide

Family

Application17/234,218Parent of this continuation · filed 19 Apr 2021
US 2023/0049039 A1Pre-grant publication · published 16 Feb 2023
US 11,489,071 B2Parent of this continuation
US 2021/0408278 A1Published application
US 11,908,929 B2This patent

From the US filing history. Foreign family members aren’t listed.

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