Low-resistance top contact on VTFET

A method for forming a semiconductor device, the method comprising:

• forming a bottom source/drain region on a semiconductor substrate;
• forming a vertical semiconductor fin including a bottom end that contacts the semiconductor substrate and is in electrical communication with the bottom source/drain region;
• forming a gate structure that wraps completely around all sidewalls the vertical semiconductor fin, wherein a top end of the vertical semiconductor fin extends above the gate structure;
• depositing an interlayer dielectric (ILD) on an upper surface of the substrate and subsequently patterning the ILD layer to form a patterned trench that expose the top end of the vertical semiconductor fin;
• forming a top source/drain region by epitaxially growing silicon within the patterned trench and from the top end of the vertical semiconductor fin and on sidewalls of the vertical semiconductor fin, the top source/drain region formed directly on an upper surface of the gate structure separated from the semiconductor substrate by the vertical semiconductor fin;
• forming an electrically conductive cap within the patterned trench and on an outer surface of the top source/drain region;
• and
• forming an electrically conductive contact via in ohmic connection with the electrically conductive cap to establish an electrically conductive path from the contact via to the bottom source/drain region,
• wherein forming an electrically conductive cap within the patterned trench comprises:
• depositing an electrically conductive film directly on sidewalls and a base of the patterned trench, and directly on exposed surfaces of the top source/drain region;
• depositing a dielectric material in the patterned trench so as to encapsulate the electrically conductive film deposited in the trench and on the top source/drain region with the dielectric material;
• and
• performing a temperature anneal process that converts the electrically conductive film formed on the top source/drain region into the electrically conductive cap that is encapsulated by the dielectric material.