Transistor isolation structures
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYu-Yun Peng, Fu-Ting Yen, Keng-Chu Lin
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYu-Yun Peng, Fu-Ting Yen, Keng-Chu Lin
Estimating the term…
The present disclosure is directed to method for the fabrication of spacer structures between source/drain (S/D) epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form cavities. Further, depositing a spacer material on the fin structure to fill the cavities and removing a portion of the spacer material in the cavities to form an opening in the spacer material. In addition, the method includes forming S/D epitaxial structures on the substrate to abut the fin structure and the spacer material so that sidewall portions of the S/D epitaxial structures seal the opening in the spacer material to form an air gap in the spacer material.
A structure, comprising:
A method, comprising:
A structure, comprising:
Dependencies are inferred from the claim text.