Passivation layer for epitaxial semiconductor process

An integrated chip, comprising:

• a substrate comprising silicon, the substrate having interior sidewalls and a recessed upper surface that form a recess within an upper surface of the substrate;
• a second semiconductor material arranged along the interior sidewalls and the recessed upper surface of the substrate, wherein the second semiconductor material comprises a group IV semiconductor or a group III-V compound semiconductor;
• a passivation layer comprising silicon, wherein the silicon of the passivation layer contacts an uppermost surface of the second semiconductor material;
• a first doped region having a first doping type and extending through the passivation layer and into the second semiconductor material;
• and
• a second doped region having a second doping type and extending through the passivation layer and into the second semiconductor material, wherein the first doped region and the second doped region are separated from a bottommost surface of the second semiconductor material by the second semiconductor material.

An integrated chip, comprising:

• a substrate comprising a first semiconductor material;
• a second semiconductor material disposed on the substrate, wherein the first semiconductor material is a different semiconductor material than the second semiconductor material;
• a passivation layer disposed on the second semiconductor material;
• a first doped region having a first doping type, the first doped region extending through the passivation layer and into the second semiconductor material, wherein the first doped region has a top that is vertically above a top of the second semiconductor material and a bottom that is vertically above a bottom of the second semiconductor material;
• and
• a second doped region having a second doping type, the second doped region extending through the passivation layer and into the second semiconductor material.