MOSFET and memory cell having improved drain current through back bias application

A method of selectively operating a semiconductor device as a semiconductor memory device or a transistor with increased on-state drain current, said method comprising:

• providing said semiconductor device comprising a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type;
• a buried layer having a second conductivity type selected from said p-type conductivity type and said n-type conductivity type and being different from said first conductivity type;
• a body having said first conductivity type;
• a source region and a drain region each having said second conductivity type and being separated by said body;
• and a gate positioned in between said source region and said drain region;
• and
• selectively operating said semiconductor device as said semiconductor memory device or said transistor, wherein said selectively operating comprises:
• applying a relatively low voltage to said buried layer to operate said semiconductor device as an ordinary transistor formed by said source region, said gate and said drain region;
• applying a relatively high voltage to said buried layer to operate said semiconductor device as said semiconductor memory device, wherein said semiconductor memory device has at least two stable states;
• and
• applying an intermediate high voltage higher than said relatively low voltage but lower than said relatively high voltage to said buried layer to operate said semiconductor device as said transistor with increased on-state drain current, said transistor with increased on-state current being formed by said source region, said gate and said drain region.