High voltage device with gate extensions
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJhih-Bin Chen, Ming Chyi Liu
Life of this patent
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Abstract
The present disclosure relates to a method of forming an integrated chip. The method includes forming a plurality of isolation structures within a substrate. The substrate is selectively etched to form a gate base recess within the substrate. The plurality of isolation structures are selectively etched to form a plurality of gate extension trenches extending outward from the gate base recess; forming a conductive material within the gate base recess and the plurality of gate extension trenches to form a gate electrode; and forming a source region and a drain region on opposing sides of the gate electrode.
Claims20
A method of forming an integrated chip, comprising:
- forming a plurality of separate isolation structures within a substrate, wherein the plurality of separate isolation structures have outermost sidewalls that face one another and that are separated from one another by the substrate;
- selectively etching the substrate to form a gate base recess within the substrate, the gate base recess extending past the outermost sidewalls of the plurality of separate isolation structures;
- selectively etching the plurality of separate isolation structures to form a plurality of gate extension trenches extending outward from the gate base recess;
- forming a conductive material within the gate base recess and the plurality of gate extension trenches to form a gate electrode;
- and
- forming a source region and a drain region on opposing sides of the gate electrode.
A method of forming an integrated chip, comprising:
- forming an isolation structure within a substrate;
- etching the substrate and the isolation structure to form a gate base recess within the substrate;
- forming a gate dielectric within the gate base recess and over the isolation structure;
- etching the gate dielectric and the isolation structure to form a gate extension trench extending outward from the gate base recess;
- forming a conductive material within the gate base recess and the gate extension trench;
- performing a planarization process to remove a part of the conductive material from over the substrate and to form a gate electrode;
- and
- forming a source region and a drain region on opposing sides of the gate electrode.
A method of forming an integrated chip, comprising:
- forming a plurality of isolation structures within a substrate, the plurality of isolation structures being separated from one another along a first direction;
- etching an upper surface of the substrate to form a gate base recess having a first depth within the substrate;
- etching the plurality of isolation structures to form a plurality of gate extension trenches having a second depth less than the first depth, wherein the plurality of gate extension trenches extend outward from the gate base recess in a second direction that is perpendicular to the first direction;
- forming a gate electrode within the gate base recess and the plurality of gate extension trenches, wherein the gate electrode is formed to have a part that is below a top of the plurality of isolation structures and that continuously extends from within the gate base recess to within the plurality of gate extension trenches;
- and
- forming a source region and a drain region on opposing sides of the gate electrode.
Dependencies are inferred from the claim text.