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US 11,908,890 B2Granted
Isolation structure for stacked vertical transistors
AssigneeInternational Business Machines Corporation
InventorsJuntao Li, Kangguo Cheng, Chen Zhang, Zhenxing Bi
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Abstract
A method for manufacturing a semiconductor device includes forming a first vertical transistor on a semiconductor substrate, and forming a second vertical transistor stacked on the first vertical transistor. In the method, an isolation layer is formed between the first and second vertical transistors. The isolation layer includes a rare earth oxide.
Claims20
A semiconductor device, comprising:
- a first vertical transistor comprising a first lower source/drain region and a first upper source/drain region disposed on a semiconductor substrate;
- a second vertical transistor comprising a second lower source/drain region and a second upper source/drain region stacked on the first vertical transistor;
- an isolation layer disposed between the first upper source/drain region of the first vertical transistor and the second lower source/drain region of the second vertical transistor;
- at least one dielectric layer distinct from the isolation layer, wherein the at least one dielectric layer is disposed on lateral sides of the isolation layer and disposed on the first vertical transistor and the second vertical transistor;
- wherein the isolation layer has a greater lateral width than a lateral width of the first upper source/drain region and a lateral width of the second lower source/drain region;
- wherein an entirety of respective ones of lateral sides of the first upper source/drain region and of the second lower source/drain region are recessed with respect to the lateral sides of the isolation layer;
- and
- wherein the isolation layer comprises a rare earth oxide.
5 more elements
A semiconductor device, comprising:
- a first vertical transistor comprising a first doping type;
- a second vertical transistor stacked on the first vertical transistor, wherein the second vertical transistor comprises a second doping type different from the first doping type;
- an isolation layer vertically stacked between source/drain regions of the first and second vertical transistors;
- and
- at least one dielectric layer distinct from the isolation layer, wherein the at least one dielectric layer is disposed on lateral sides of the isolation layer and disposed on the first vertical transistor and the second vertical transistor;
- wherein the isolation layer has a greater lateral width than lateral widths of the source/drain regions of the first and second vertical transistors;
- wherein an entirety of respective ones of lateral sides of the source/drain regions of the first and second vertical transistors are recessed with respect to the lateral sides of the isolation layer;
- and
- wherein the isolation layer comprises a rare earth oxide.
6 more elements
Dependencies are inferred from the claim text.