Gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof

A method comprising:

• forming a gate dielectric layer in a gate opening, wherein the gate opening exposes a first transistor region, a second transistor region, and a boundary region between the first transistor region and the second transistor region;
• depositing a first work function layer in the gate opening, wherein the first work function layer is disposed over the gate dielectric layer in the first transistor region, the second transistor region, and the boundary region;
• after removing the first work function layer from the first transistor region, depositing a second work function layer in the gate opening, wherein the second work function layer is disposed over the gate dielectric layer in the first transistor region and the first work function layer in the second transistor region and the boundary region;
• after removing the second work function layer from the first transistor region and the second transistor region, depositing a third work function layer in the gate opening, wherein the third work function layer is disposed over the gate dielectric layer in the first transistor region, the first work function layer in the second transistor region, and the second work function layer in the boundary region;
• and
• depositing a fourth work function layer in the gate opening, wherein the fourth work function layer is disposed over the third work function layer in the first transistor region and the third work function layer in the second transistor region;
• and
• performing a planarization process to remove excess of the first work function layer, the second work function layer, the third work function layer, and the fourth work function layer.

A method comprising:

• forming a gate opening that extends lengthwise along a first direction and widthwise along a second direction, wherein the gate opening extends along the first direction and exposes a first semiconductor channel for a first transistor, a second semiconductor channel for a second transistor, and a dielectric structure, wherein the dielectric structure is between the first semiconductor channel and the second semiconductor channel, the first semiconductor channel extends between first source/drains along the second direction, and the second semiconductor channel extends between second source/drains along the second direction;
• depositing a gate dielectric layer over the first semiconductor channel, the second semiconductor channel, and the dielectric structure;
• depositing a first p-type work function layer over the first semiconductor channel, the second semiconductor channel, and the dielectric structure;
• depositing a second p-type work function layer over the first semiconductor channel, the second semiconductor channel, and the dielectric structure;
• depositing a third p-type work function layer over the first semiconductor channel, the second semiconductor channel, and the dielectric structure;
• depositing an n-type work function layer over the first semiconductor channel, the second semiconductor channel, and the dielectric structure;
• wherein the first p-type work function layer is removed from over the first semiconductor channel before the depositing the second p-type work function layer;
• wherein the second p-type work function layer is removed from over the first semiconductor channel and the second semiconductor channel before depositing the third p-type work function layer;
• and
• wherein:
• over the first semiconductor channel, the gate dielectric layer, the third p-type work function layer, and the n-type work function layer fill the gate opening along the second direction,
• over the second semiconductor channel, the gate dielectric layer, the first p-type work function layer, the third p-type work function layer, and the n-type work function layer fill the gate opening along the second direction, and
• over a portion of the dielectric structure, the gate dielectric layer, the first p-type work function layer, the second p-type work function layer, and the third p-type work function layer fill the gate opening along the second direction.