Integrated chip with improved latch-up immunity

An integrated chip (IC) comprising:

• a first semiconductor fin protruding from a portion of a semiconductor substrate;
• a second semiconductor fin protruding from the portion of the semiconductor substrate, wherein the second semiconductor fin is laterally spaced from the first semiconductor fin in a first direction;
• a gate structure disposed over the portion of the semiconductor substrate and the first semiconductor fin, wherein the gate structure extends laterally over the semiconductor substrate and the first semiconductor fin in a second direction that is transverse the first direction;
• and
• an epitaxial pick-up structure disposed on the second semiconductor fin, wherein the epitaxial pick-up structure continuously extends from a first outermost sidewall of the second semiconductor fin to a second outermost sidewall of the second semiconductor fin, and wherein the second outermost sidewall is laterally spaced from the first outermost sidewall in the first direction.

An integrated chip (IC) comprising a device section and a pick-up section disposed on a side of the device section, the IC comprising:

• an isolation structure disposed over a lower portion of a semiconductor substrate;
• a first semiconductor fin disposed in the device section, wherein the first semiconductor fin extends vertically through the isolation structure from the lower portion of the semiconductor substrate;
• a second semiconductor fin disposed in the pick-up section, wherein the second semiconductor fin extends vertically through the isolation structure from the lower portion of the semiconductor substrate, wherein the second semiconductor fin has a first outer sidewall that faces an outer sidewall of the first semiconductor fin, and wherein a portion of the isolation structure extends laterally from the outer sidewall of the first semiconductor fin to the first outer sidewall of the second semiconductor fin;
• a doped region disposed in the first semiconductor fin, the second semiconductor fin, and the lower portion of the semiconductor substrate, wherein the doped region extends from the first semiconductor fin to the second semiconductor fin by extending beneath the portion of the isolation structure;
• a pair of source/drain regions disposed in the first semiconductor fin;
• a gate structure disposed over the first semiconductor fin and the lower portion of the semiconductor substrate, wherein the gate structure extends laterally over the semiconductor substrate and the first semiconductor fin in a first direction, wherein the gate structure extends laterally in the first direction between the source/drain regions of the pair of source/drain regions, and wherein the gate structure is laterally spaced from the second semiconductor fin;
• and
• an epitaxial pick-up structure disposed on the second semiconductor fin, wherein the epitaxial pick-up structure is electrically coupled to the doped region, wherein the epitaxial pick-up structure continuously extends from the first outer sidewall of the second semiconductor fin to a second outer sidewall of the second semiconductor fin, and wherein the second outer sidewall of the second semiconductor fin is opposite the first outer sidewall of the second semiconductor fin.