Semiconductor device including transistors sharing gates with structures having reduced parasitic circuit

A semiconductor device, comprising:

• a first metal contact configured to have a first voltage level;
• a second metal contact configured to have a second voltage level;
• a first gate disposed between two terminals of the first metal contact, and disposed between two terminals of the second metal contact;
• a second gate disposed between the first gate and a first terminal of the two terminals of the first metal contact, and disposed between the first gate and a first terminal of the two terminals of the second metal contact;
• and
• a third metal contact disposed between the first gate and the second gate, and disconnected from the first metal contact and the second metal contact.

A semiconductor device, comprising:

• a first transistor, wherein a first terminal of the first transistor is configured to receive a first voltage signal;
• a second transistor, wherein a first terminal of the second transistor is configured to receive a second voltage signal, a second terminal of the second transistor is coupled to a control terminal of the first transistor, and a control terminal of the second transistor is coupled to a second terminal of the first transistor;
• a third transistor, wherein a first terminal of the third transistor is configured to receive the first voltage signal;
• and
• a fourth transistor, wherein a first terminal of the fourth transistor is configured to receive the second voltage signal, a second terminal of the fourth transistor is coupled to a second terminal of the third transistor, and a control terminal of the fourth transistor is configured to receive the second voltage signal through a first resistor.