Integrated circuit and method of generating integrated circuit layout

An integrated circuit, comprising:

• a cell layer including a first cell and a second cell;
• a first metal layer over the cell layer, comprising:
• a first conductive feature vertically over the first cell and having a linear top profile;
• a second conductive feature vertically over the second cell and having a linear top profile;
• and
• a third conductive feature having a portion non-overlapping the first and second cells, and having an L-shape top profile;
• a first via connecting the first conductive feature and the first cell;
• and
• a second via connecting the second conductive feature and the second cell.

An integrated circuit, comprising:

• a cell layer including a first cell and a second cell separated by a non-zero distance;
• a first metal layer over the cell layer, comprising:
• a first conductive feature overlapping the first cell and having a lengthwise direction along a first direction;
• and
• a second conductive feature overlapping the second cell and having a lengthwise direction along the first direction;
• a second metal layer over the first metal layer, comprising a third conductive feature overlapping both the first and second cells and having a lengthwise direction along the first direction;
• and
• a third metal layer between the first and second metal layers, wherein the third metal layer comprises a fourth conductive feature electrically connecting the first and third conductive features, and a fifth conductive feature electrically connecting the second and third conductive features.