Back emission display

A back emission display backplane comprising:

• a transparent substrate with a top surface;
• a power interface layer having a bottom surface overlying the substrate top surface, a top surface with a plurality of first electrical contacts and a plurality of second electrical contacts, and a plurality of apertures, each aperture formed with a top surface adjacent to the transparent substrate and the bottom surface adjacent to an emission layer;
• and,
• the emission layer having a bottom surface overlying the power interface layer top surface and comprising a plurality of sub-pixel regions, each sub-pixel region comprising a well overlying a corresponding aperture, a first conductive via electrically connected to a corresponding first electrical contact, and a second conductive via electrically connected to a corresponding second electrical contact.

A back emission display comprising:

• a transparent substrate with a top surface;
• a power interface layer having a bottom surface overlying the substrate top surface, a top surface with a plurality of first electrical contacts and a plurality of second electrical contacts, and a plurality of apertures, each aperture formed with a top surface adjacent to the transparent substrate and the bottom surface adjacent to an emission layer;
• the emission layer having a bottom surface overlying the power interface layer top surface comprising a plurality of sub-pixel regions, each sub-pixel region comprising a well overlying a corresponding aperture, a first conductive via electrically connected to a corresponding first electrical contact, and a second conductive via electrically connected to a corresponding second electrical contact;
• a back emission micro-light emitting diode (microLED) occupying each well, having an emissive bottom surface overlying a corresponding aperture, a first electrode formed on a microLED top surface, and a second electrode formed on the microLED top surface;
• a first electrical interconnect formed on an emission layer top surface electrically connecting each first conductive via to a corresponding microLED first electrode;
• an insulating layer overlying the emission layer top surface and comprising a third conductive via electrically connected to a corresponding second conductive via on the emission layer top surface and a fourth conductive via electrically connected to a corresponding microLED second electrode;
• and,
• a second electrical interconnect formed on an insulating layer top surface electrically connecting each third conductive via to a corresponding fourth conductive via.

A method for fabricating a back emission micro light emitting diode (microLED), the method comprising:

• providing a metalorganic chemical vapor deposition (MOCVD) structure comprising a first doped semiconductor overlying a growth substrate, with a top surface in a second plane, a multiple quantum well (MQW) layer overlying the first doped semiconductor having a top surface in a third plane, and a second doped semiconductor overlying the MQW layer and having a top surface in a fourth plane, where the first and second doped semiconductors are oppositely doped with n and p type dop ants;
• etching the MOCVD structure to form a plurality of microLEDs;
• selectively etching a MOCVD stack to form emitter areas by removing regions of the second doped semiconductor and MQW layer, and partially removing regions of the first doped semiconductor to the level of a first plane underlying the second plane;
• conformally depositing an electrical insulator overlying the MOCVD stack;
• selectively etching the electrical insulator overlying the etched regions of the MOCVD stack creating a perimeter via;
• forming a perimeter electrode having a ring shape overlying the first via and having a substrate interface surface in at least a fifth plane;
• etching an opening in the electrical insulator in the unetched regions of the MOCVD stack, creating a center via;
• forming a center electrode overlying the center via, at least partially surrounded by the perimeter electrode, and having a substrate interface surface in a sixth plane;
• and,
• separating the fabricated microLEDs from the growth substrate.

A method for fabricating a back emission backplane, the method comprising:

• providing a transparent substrate with a top surface;
• depositing a first dielectric layer having a bottom surface overlying the substrate top surface;
• forming a power interface layer from the first dielectric layer, including a first plurality of first electrical contacts, a first plurality of second electrical contacts, and a first plurality of apertures, each aperture formed with a top surface adjacent to the transparent substrate and a bottom surface adjacent to a second dielectric laver;
• depositing the second dielectric layer having the bottom surface overlying the power interface layer top surface;
• forming an emission layer from the second dielectric layer including a first plurality of sub-pixel regions, forming each sub-pixel as follows:
• patterning the emission layer to form a well overlying a corresponding aperture, a first via overlying a corresponding first electrical contact, and a second via overlying a corresponding second electrical contact;
• depositing an electrically conductive metal in the emission layer first and second vias;
• and,
• positioning back emission micro-light emitting diodes (microLEDs) with an emissive bottom surface interfacing a corresponding aperture.

A method for fabricating a back emission micro light emitting diode (microLED), the method comprising:

• providing a metalorganic chemical vapor deposition (MOCVD) structure comprising a first doped semiconductor overlying a growth substrate, with a top surface in a second plane, a multiple quantum well (MQW) layer overlying the first doped semiconductor having a top surface in a third plane, and a second doped semiconductor overlying the MQW layer and having a top surface in a fourth plane, where the first and second doped semiconductors are oppositely doped with n and p type dopants;
• etching the MOCVD structure to form a plurality of microLEDs;
• selectively etching a MOCVD stack to form emitter areas by removing regions of the second doped semiconductor and MQW layer, and partially removing regions of the first doped semiconductor to the level of a first plane underlying the second plane;
• conformally depositing an electrical insulator overlying the MOCVD stack;
• selectively etching the electrical insulator creating a perimeter via and a center via;
• conformally depositing a strike layer, forming a center electrode in a sixth plane overlying the center via;
• etching openings to expose the strike layer overlying the center via;
• filling the etched opening with metal to form an electrically conductive orientation keel overlying the strike layer center electrode;
• forming a perimeter electrode have a substrate surface in at least a fifth plane overlying the first via;
• and,
• separating the fabricated microLEDs from the growth substrate.

A back emission micro-light emitting diode (microLED) comprising:

• a first semiconductor layer doped with a dopant selected from the dopant group consisting of n and p type dopants, the first doped semiconductor layer having a first top surface formed in a first plane and a second top surface formed in an overlying second plane, and having a bottom emission surface;
• a multiple quantum well (MQW) layer having a top surface formed in a third plane, overlying the first doped semiconductor second top surface;
• a second semiconductor doped with the unselected dopant type from the dopant group, formed as a layer having a top surface in a fourth plane, overlying the MQW layer;
• an electrical insulator overlying the top surface of the second doped semiconductor and the first top surface of the first doped semiconductor;
• a first electrode overlying and connected to the first doped semiconductor first top surface through a first via, and having a substrate interface surface in at least a fifth plane;
• a second electrode overlying and connected to the second doped semiconductor through a second via, and having a substrate interface surface in a sixth plane;
• and,
• wherein an electrode selected from the group consisting of the first electrode and the second electrode is formed as a ring at least partially surrounding an unselected electrode.

A back emission display comprising:

• a transparent substrate with a top surface;
• a power interface layer having a bottom surface overlying the substrate top surface, a top surface with a plurality of first electrical contacts and a plurality of second electrical contacts, and a plurality of apertures formed between a top surface and the bottom surface;
• an emission layer having a bottom surface overlying the power interface layer top surface comprising a plurality of sub-pixel regions, each sub-pixel region comprising a well overlying a corresponding aperture, a first conductive via electrically connected to a corresponding first electrical contact, and a second conductive via electrically connected to a corresponding second electrical contact;
• a back emission micro-light emitting diode (microLED) occupying each well, having an emissive bottom surface overlying a corresponding aperture, a first electrode formed on a microLED top surface, and a second electrode formed on the microLED top surface;
• a first electrical interconnect formed on an emission layer top surface electrically connecting each first conductive via to a corresponding microLED first electrode;
• an insulating layer overlying the emission layer top surface and comprising a third conductive via electrically connected to a corresponding second conductive via on the emission layer top surface and a fourth conductive via electrically connected to a corresponding microLED second electrode;
• a second electrical interconnect formed on an insulating layer top surface electrically connecting each third conductive via to a corresponding fourth conductive via;
• wherein each microLED further comprises an electrically conductive orientation keel electrically connected to, and overlying the second electrode;
• and,
• wherein the fourth conductive via is the orientation keel.

A back emission display backplane comprising:

• a transparent substrate with a top surface;
• a power interface layer having a bottom surface overlying the substrate top surface, a top surface with a plurality of first electrical contacts and a plurality of second electrical contacts, and a plurality of apertures formed between a top surface and the bottom surface;
• an emission layer having a bottom surface overlying the power interface layer top surface and comprising a plurality of sub-pixel regions, each sub-pixel region comprising a well overlying a corresponding aperture, a first conductive via electrically connected to a corresponding first electrical contact, and a second conductive via electrically connected to a corresponding second electrical contact;
• and,
• wherein each first conductive via in the emissive layer is formed as a ring overlying a corresponding first electrical contact.

A back emission display comprising:

• a transparent substrate with a top surface;
• a power interface layer having a bottom surface overlying the substrate top surface, a top surface with a plurality of first electrical contacts and a plurality of second electrical contacts, and a plurality of apertures formed between a top surface and the bottom surface;
• an emission layer having a bottom surface overlying the power interface layer top surface comprising a plurality of sub-pixel regions, each sub-pixel region comprising a well overlying a corresponding aperture, a first conductive via electrically connected to a corresponding first electrical contact, and a second conductive via electrically connected to a corresponding second electrical contact;
• a back emission micro-light emitting diode (microLED) occupying each well, having an emissive bottom surface overlying a corresponding aperture, a first electrode formed on a microLED top surface, and a second electrode formed on the microLED top surface;
• a first electrical interconnect formed on an emission layer top surface electrically connecting each first conductive via to a corresponding microLED first electrode;
• an insulating layer overlying the emission layer top surface and comprising a third conductive via electrically connected to a corresponding second conductive via on the emission layer top surface and a fourth conductive via electrically connected to a corresponding microLED second electrode;
• a second electrical interconnect formed on an insulating layer top surface electrically connecting each third conductive via to a corresponding fourth conductive via;
• and,
• wherein each first conductive via in the emissive layer is formed as a ring surrounding the well and overlying a corresponding first electrical contact.

A method for fabricating a back emission micro light emitting diode (microLED), the method comprising:

• providing a metalorganic chemical vapor deposition (MOCVD) structure comprising a first doped semiconductor overlying a growth substrate, with a top surface in a second plane, a multiple quantum well (MQW) layer overlying the first doped semiconductor having a top surface in a third plane, and a second doped semiconductor overlying the MQW layer and having a top surface in a fourth plane, where the first and second doped semiconductors are oppositely doped with n and p type dop ants;
• etching the MOCVD structure to form a plurality of microLEDs;
• selectively etching a MOCVD stack to form emitter areas by removing regions of the second doped semiconductor and MQW layer, and partially removing regions of the first doped semiconductor to the level of a first plane underlying the second plane;
• conformally depositing an electrical insulator overlying the MOCVD stack;
• selectively etching the electrical insulator overlying the etched regions of the MOCVD stack creating a perimeter via;
• forming a perimeter electrode overlying the first via having a substrate interface surface in at least a fifth plane;
• etching an opening in the electrical insulator in the unetched regions of the MOCVD stack, creating a center via;
• forming a center electrode overlying the center via, having a substrate interface surface in a sixth plane;
• forming an electrically conductive orientation keel overlying the center electrode;
• and,
• separating the fabricated microLEDs from the growth substrate.

A method for fabricating a back emission backplane, the method comprising:

• providing a transparent substrate with a top surface;
• for each sub-pixel, forming a control circuit overlying the transparent substrate top surface, having a first electrical interface and a second electrical interface;
• depositing a first dielectric layer having a bottom surface overlying the substrate top surface;
• forming a power interface layer from the first dielectric layer, including a first plurality of first electrical contacts, a first plurality of second electrical contacts, and a first plurality of apertures formed between the top surface and the bottom surface;
• depositing a second dielectric layer having a bottom surface overlying the power interface layer top surface;
• forming an emission layer from the second dielectric layer including a first plurality of sub-pixel regions, forming each sub-pixel as follows:
• patterning the emission layer to form a well overlying a corresponding aperture, a first via overlying a corresponding first electrical contact, and a second via overlying a corresponding second electrical contact;
• depositing an electrically conductive metal in the emission layer first and second vias;
• positioning back emission micro-light emitting diodes (microLEDs) with an emissive bottom surface interfacing a corresponding aperture;
• wherein forming the power interface layer includes:
• etching a third via overlying the electrical control circuit first electrical interface and a fourth via overlying the electrical control circuit second electrical interface;
• and,
• filling the third via with an electrically conductive metal and forming the second electrical contact overlying the third via, and filling the fourth via with the electrically conductive metal and forming a power signal line overlying the fourth via.

A method for fabricating a back emission backplane, the method comprising:

• providing a transparent substrate with a top surface;
• depositing a first dielectric layer having a bottom surface overlying the substrate top surface;
• forming a power interface layer from the first dielectric layer, including a first plurality of first electrical contacts, a first plurality of second electrical contacts, and a first plurality of apertures formed between the top surface and the bottom surface;
• depositing a second dielectric layer having a bottom surface overlying the power interface layer top surface;
• forming an emission layer from the second dielectric layer including a first plurality of sub-pixel regions, forming each sub-pixel as follows:
• patterning the emission layer to form a well overlying a corresponding aperture, a first via overlying a corresponding first electrical contact, and a second via overlying a corresponding second electrical contact;
• depositing an electrically conductive metal in the emission layer first and second vias;
• positioning back emission micro-light emitting diodes (microLEDs) with an emissive bottom surface interfacing a corresponding aperture;
• wherein patterning the emission layer includes patterning the second via in a ring shape surrounding the well;
• and,
• wherein depositing metal in the emission layer vias includes filling the second via ring with an optically reflective metal.

A method for fabricating a back emission backplane, the method comprising:

• providing a transparent substrate with a top surface;
• depositing a first dielectric layer having a bottom surface overlying the substrate top surface;
• forming a power interface layer from the first dielectric layer, including a first plurality of first electrical contacts, a first plurality of second electrical contacts, and a first plurality of apertures formed between the top surface and the bottom surface;
• depositing a second dielectric layer having a bottom surface overlying the power interface layer top surface;
• forming an emission layer from the second dielectric layer including a first plurality of sub-pixel regions, forming each sub-pixel as follows:
• patterning the emission layer to form a well overlying a corresponding aperture, a first via overlying a corresponding first electrical contact, and a second via overlying a corresponding second electrical contact;
• depositing an electrically conductive metal in the emission layer first and second vias;
• positioning back emission micro-light emitting diodes (microLEDs) with an emissive bottom surface interfacing a corresponding aperture;
• and,
• wherein positioning the back emission microLEDs includes positioning microLEDs with orientation keels using a fluidic assembly process.

A back emission display backplane comprising:

• a transparent substrate with a top surface;
• a power interface layer having a bottom surface overlying the substrate top surface, a top surface with a plurality of first electrical contacts and a plurality of second electrical contacts, and a plurality of apertures formed between a top surface and the bottom surface;
• an emission layer having a bottom surface overlying the power interface layer top surface and comprising a plurality of sub-pixel regions, each sub-pixel region comprising a well overlying a corresponding aperture, a first conductive via electrically connected to a corresponding first electrical contact, and a second conductive via electrically connected to a corresponding second electrical contact;
• wherein the power interface layer further comprises:
• a plurality of control circuits, each control circuit having a first interface electrically connected to a corresponding second electrical contact, and a second interface;
• an electrically conductive power signal line formed in the power interface layer top surface and electrically connected to the control circuit second interface;
• and,
• an electrically conductive column line formed in the power interface layer top surface and electrically connected to a first electrical contact.