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US 11,908,821 B2Granted
Sacrificial dielectric for lithographic via formation to enable via scaling in high density interconnect packaging
AssigneeIntel Corporation
InventorsKristof Darmawikarta, Sri Ranga Sai Boyapati, Hiroki Tanaka, Robert A. May
Life of this patent
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Abstract
An apparatus, comprising a substrate comprising a dielectric, a conductor, comprising a via embedded within the dielectric, the via has a first end and a second end, and substantially vertical sidewalls between the first end and the second end, and a conductive structure extending laterally from the first end of the via over the dielectric, wherein the via and the conductive structure have a contiguous microstructure.
Claims19
An integrated circuit (IC) package, comprising:
- a level of metallization structures spaced apart within an area of the package;
- a dielectric material over the level of metallization structures, wherein a first of the level of metallization structures comprises a bond pad on an embedded multichip interconnect bridge (EMIB) embedded within the dielectric material;
- a plurality of first bond pad structures within the area of the package, wherein each of the first bond pad structures extends over a portion of the dielectric material, and comprises an integral via that is adjacent to a sidewall of the dielectric material and is in contact with a corresponding one of the level of metallization structures;
- an IC die comprising a plurality of second bond pad structures within an area of the IC die;
- and
- a plurality of interconnect structures that couple the first bond pad structures to the second bond pad structures.
3 more elements
A system comprising:
- an integrated circuit (IC) package comprising:
- an embedded multichip interconnect bridge (EMIB);
- a plurality of levels of package metallization structures adjacent to the EMIB, and embedded within a first package dielectric material;
- a second package dielectric material over the first package dielectric material and the levels of package metallization structures, and over the EMIB;
- a plurality of first bond pad structures, wherein each of the first bond pad structures extends over a portion of the second package dielectric material, and comprises an integral via that is adjacent to a sidewall of the second package dielectric material, and wherein a first of the first bond pad structures is in contact with a top level of the package metallization structures, and wherein a second of the first bond pad structures is in contact with a metallization structure of the EMIB;
- an IC die comprising a plurality of second bond pad structures;
- and
- a plurality of interconnect structures that couple the first bond pad structures to the second bond pad structures.
5 more elements
Dependencies are inferred from the claim text.