Semiconductor package and method of fabricating the same

A semiconductor package, comprising:

• a first substrate that includes a first insulating layer, and a ground pattern and a first conductive pattern inside the first insulating layer;
• a first semiconductor chip placed on an upper surface of the first substrate;
• a ball array structure that is placed on the upper surface of the first substrate, is electrically connected to the ground pattern, extends along a perimeter of the first semiconductor chip and is adjacent to the first semiconductor chip;
• and
• a shielding structure that is placed on an upper surface of the first semiconductor chip and is in contact with at least a part of an upper surface of the ball array structure,
• wherein the ball array structure has a closed loop shape and includes a material that differs from that of the shielding structure.

A semiconductor package, comprising:

• a first substrate that includes a first insulating layer, a ground pattern in the first insulating layer, and a first conductive pattern;
• a first semiconductor chip placed on an upper surface of the first substrate;
• a ball array structure placed on the upper surface of the first substrate and adjacent to the first semiconductor chip, wherein the ball array structure is electrically connected to the ground pattern, extends along a perimeter of the first semiconductor chip, and has a closed loop shape;
• a shielding structure disposed on an upper surface of the first semiconductor chip, wherein the shielding structure is in contact with at least a part of an upper surface of the ball array structure and the upper surface of the first semiconductor chip;
• an interposer placed on the shielding structure wherein the interposer includes a second insulating layer and a second conductive pattern placed in the second insulating layer;
• a connection terminal placed between the first substrate and the interposer wherein the connection terminal electrically connects the first conductive pattern and the second conductive pattern;
• a second substrate placed on the interposer;
• and
• a second semiconductor chip placed on the second substrate wherein the second semiconductor chip is electrically connected to the first substrate through the second substrate, the interposer, and the connection terminal,
• wherein the ball array structure includes a solder ball portion that is spaced apart from the first semiconductor chip, and a connecting portion that connects adjacent solder ball portions,
• a maximum width in a first direction parallel to the upper surface of the first substrate of the solder ball portion is greater than a maximum width of the connecting, portion in a direction perpendicular to an extension direction of the connecting portion between adjacent solder ball portions, and is greater than a maximum width of the connection terminal, in the first direction, and
• the shielding structure includes a material that differs from that of the ball array structure.