Array substrate and display panel

A display panel, comprising:

• an array substrate, wherein the array substrate comprises:
• a base;
• a first metal layer formed on the base;
• wherein the first metal layer is patterned to form a first metal line and a first alignment identification terminal, the first metal line comprises a first gate signal line and a second gate signal line;
• a second metal layer formed on the first metal layer;
• wherein the second metal layer is patterned to form a second metal line and a second alignment identification terminal, the second metal line comprises a first data signal line, a second data signal line, a signal connection line, and a third data signal line;
• and
• a pixel electrode layer formed on the second metal layer, wherein the pixel electrode layer is patterned to form a pixel electrode, and the pixel electrode comprises a first sub-pixel electrode and a second sub-pixel electrode, and the first sub-pixel electrode and the second sub-pixel electrode each has four domains;
• wherein the first alignment identification terminal is integrally formed with the second gate signal line, wherein the first alignment identification terminal is used for alignment identification in the array substrate, and to transfer gate signals;
• wherein the second alignment identification terminal is integrally formed with the third data signal line, wherein the second alignment identification terminal is used for alignment identification in the array substrate, and to transfer data signals;
• wherein the first alignment identification terminal and the second alignment identification terminal are disposed opposite with each other, and projections of the first alignment identification terminal and the second alignment identification terminal on the base coincide;
• wherein first portions of the first alignment identification terminal and the second alignment identification terminal are disposed in the first sub-pixel electrode, second portions of the first alignment identification terminal and the second alignment identification terminal are disposed in the second sub-pixel electrode, and central portions of the first alignment identification terminal and the second alignment identification terminal are disposed in a non-pixel electrode region between the first sub-pixel electrode and the second sub-pixel electrode.