Semiconductor structure

A semiconductor structure comprising:

• a multi-level interconnect structure;
• a passivation layer above the multi-level interconnect structure;
• a pad layer partially in the passivation layer and above the multi-level interconnect structure;
• and
• a barrier layer between the multi-level interconnect structure and the pad layer, wherein the barrier layer comprises:
• a first tantalum-containing layer;
• a second tantalum-containing layer above the first tantalum-containing layer;
• and
• a third tantalum-containing layer above the second tantalum-containing layer, wherein the first tantalum-containing layer and the third tantalum-containing layer have nitrogen concentrations higher than that of the second tantalum-containing layer, and threading dislocation defects in the first tantalum-containing layer are misaligned with threading dislocation defects of the third tantalum-containing layer.

A semiconductor structure comprising:

• an inter-metal dielectric layer;
• a conductive line embedded in the inter-metal dielectric layer;
• a passivation layer over the inter-metal dielectric layer and covering a portion of the conductive line;
• a pad layer partially embedded in the passivation layer and over the conductive line;
• and
• a barrier layer between the pad layer and the conductive line, wherein the barrier layer comprises:
• a first layer in a nano-crystalline phase;
• a second layer above the first layer and in a poly-crystalline phase;
• a third layer above the second layer and in the nano-crystalline phase;
• and
• a fourth layer above the third layer and in the poly-crystalline phase.