Semiconductor integrated circuit device

A semiconductor integrated circuit device including a standard cell as a capacitance cell, the standard cell comprising:

• a first power supply line extending in a first direction and supplying a first power supply voltage;
• a second power supply line extending in the first direction and supplying a second power supply voltage different from the first power supply voltage;
• a capacitance part provided between the first power supply line and the second power supply line as viewed in plan;
• and
• a fixed-value output part provided between the first power supply line and the second power supply line as viewed in plan, for supplying the first power supply voltage or the second power supply voltage to the capacitance part,
• wherein
• the capacitance part has
• a first transistor that is a three-dimensional transistor, and
• a second transistor that is a three-dimensional transistor of the same conductivity type as the first transistor, formed above the first transistor in a depth direction,
• a source and drain of the first transistor and a source and drain of the second transistor are all connected to one of the first and second power supply lines,
• the fixed-value output part has
• a third transistor that is a three-dimensional transistor of the first conductivity type, formed on a level with the first transistor in the depth direction, and
• a fourth transistor that is a three-dimensional transistor of a second conductivity type different from the first conductivity type, formed on a level with the second transistor in the depth direction,
• a source of the third transistor is connected to the first power supply line and a drain thereof is connected to a gate of the fourth transistor, and a source of the fourth transistor is connected to the second power supply line and a drain thereof is connected to a gate of the third transistor,
• gates of the first and second transistors are both connected to the gate of the third transistor or the gate of the fourth transistor, and
• a dummy gate interconnect is placed between the first and second transistors and the third and fourth transistors.

A semiconductor integrated circuit device including a first standard cell and a second standard cell that is a capacitance cell, the first standard cell comprising:

• a first power supply line extending in a first direction and supplying a first power supply voltage;
• a second power supply line extending in the first direction and supplying a second power supply voltage different from the first power supply voltage;
• a first transistor that is a three-dimensional transistor of a first conductivity type;
• a second transistor that is a three-dimensional transistor of a second conductivity type, formed above the first transistor in a depth direction;
• a first local interconnect connected with a source or drain of the first transistor, extending in a second direction perpendicular to the first direction as viewed in plan;
• a second local interconnect connected with a source or drain of the second transistor, extending in the second direction as viewed in plan;
• and
• a first gate interconnect that is to be a common gate of the first and second transistors, extending in the second direction as viewed in plan,
• the second standard cell comprising:
• a second gate interconnect formed on a level with the first gate interconnect in the depth direction;
• a third local interconnect formed on a level with the first local interconnect in the depth direction;
• and
• a fourth local interconnect formed on a level with the second local interconnect in the depth direction,
• wherein
• the second gate interconnect is electrically connected with one of the first and second power supply lines, and the third and fourth local interconnects are electrically connected with the other of the first and second power supply lines, and
• the third and fourth local interconnects overlap each other as viewed in plan and are adjacent to the second gate interconnect as viewed in plan.