Protection liner on interconnect wire to enlarge processing window for overlying interconnect via

An integrated chip comprising:

• a substrate;
• a first interconnect dielectric layer disposed over the substrate;
• an interconnect wire arranged in the first interconnect dielectric layer, the interconnect wire having a base wire portion with a base wire width and an upper wire portion with an upper wire width, wherein the upper wire width is narrower than the base wire width such that the interconnect wire has tapered outer wire sidewalls;
• a second interconnect dielectric layer disposed over the interconnect wire;
• and
• an interconnect via disposed over the interconnect wire, the interconnect via having a base via portion with a base via width and an upper via portion with an upper via width, wherein the upper via width is wider than the base via width such that the interconnect via has tapered outer via sidewalls;
• and
• wherein the interconnect via includes a protrusion that extends asymmetrically from the base via portion and is coupled to the upper wire portion of the interconnect via.

A method comprising:

• forming an interconnect wire over a substrate;
• forming a protection liner on outer surfaces of the interconnect wire;
• forming a first interconnect dielectric layer around the interconnect wire;
• forming a first etch stop layer selectively on the first interconnect dielectric layer and not on the protection liner;
• and
• forming an interconnect via contacting an upper surface of the protection liner and coupled to the interconnect wire through the protection liner.