Partial subtractive supervia enabling hyper-scaling
AssigneeInternational Business Machines Corporation
InventorsSagarika Mukesh, Nicholas Anthony Lanzillo
Life of this patent
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Abstract
A semiconductor device includes an upper section of a supervia formed via subtractive etching and a lower section of the supervia formed via damascene processing. The supervia connects non-adjacent interconnect wiring. The lower section and the upper section of the supervia each define a generally cone-shaped configuration. A distal end of the lower section of the supervia is non-obtuse. Moreover, the lower section of the supervia is formed in a V0 level and the upper section of the supervia is formed in a M1/V1 metallization level.
Claims17
A semiconductor device comprising:
- an upper section of a supervia, formed via subtractive etching, that defines a generally cone-shaped configuration;
- and
- a lower section of the supervia, formed via damascene processing, that defines a generally cone-shaped configuration,
- wherein the supervia connects non-adjacent interconnect wiring.
A semiconductor device comprising:
- an upper section of a supervia, formed via subtractive etching, that defines a generally cone-shaped configuration;
- and
- a lower section of the supervia formed, via damascene processing, that defines a generally cone-shaped configuration,
- wherein a maximum width of the upper section of the supervia is greater than a maximum width of the lower section of the supervia.
A method comprising:
- forming an upper section of a supervia via subtractive etching to define a generally cone-shaped configuration of the upper section;
- forming a lower section of the supervia via damascene processing to define a generally cone-shaped configuration of the lower section;
- and
- enabling the supervia to connect non-adjacent interconnect wiring.
Dependencies are inferred from the claim text.