3D IC decoupling capacitor structure and method for manufacturing the same

A semiconductor structure, comprising:

• a first redistribution layer (RDL);
• a molding layer over the first RDL;
• a metal-insulator-metal (MIM) capacitor vertically passing through the molding layer, the MIM capacitor including a first electrode, an insulation layer and a second electrode, wherein an outer sidewall and an outer bottom surface of the first electrode is lined with the insulation layer, and an outer sidewall and an outer bottom surface of the insulation layer is lined with the second electrode, and the insulation layer protrudes upward from a top surface of the first electrode;
• and
• a device die in the molding layer, wherein the device die includes a conductive pillar having a top surface substantially aligned with the top surface of the first electrode.

A semiconductor structure, comprising:

• a molding layer;
• and
• a first metal electrode extending into the molding layer;
• an insulation layer surrounding an outer sidewall and an outer bottom surface of the first metal electrode;
• a second metal electrode surrounding an outer sidewall and an outer bottom surface of the insulation layer;
• wherein the insulation layer protrudes upward from a top surface of the first metal electrode;
• and
• a device die in the molding layer, wherein the device die includes a conductive pillar having a top surface substantially aligned with the top surface of the first metal electrode.