Semiconductor package including dual stiffener
AssigneeSamsung Electronics Co., Ltd.
InventorsHeungkyu Kwon, Junso Pak, Heeseok Lee
Life of this patent
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Abstract
A semiconductor package includes; a dual stiffener including an upper stiffener and a lower stiffener, an upper package including an upper package substrate, a semiconductor chip centrally mounted on an upper surface of the upper package substrate, and the upper stiffener disposed along an outer edge of the upper package substrate, and a lower package substrate that centrally mounts the upper package and includes the lower stiffener disposed on an upper surface of the lower package substrate to surround the upper package substrate.
Claims18
A semiconductor package comprising:
- a dual stiffener including an upper stiffener and a lower stiffener;
- an upper package including an upper package substrate, a semiconductor chip centrally mounted on an upper surface of the upper package substrate, and the upper stiffener disposed along an outer edge of the upper package substrate;
- and
- a lower package substrate that centrally mounts the upper package and includes the lower stiffener disposed on an upper surface of the lower package substrate to surround the upper package substrate;
- and
- passive elements disposed in at least one of the upper surface of the upper package substrate between the semiconductor chip and the upper stiffener, and a central portion of a lower surface of the lower package substrate.
A semiconductor package comprising:
- a dual stiffener including an upper stiffener and a lower stiffener;
- an upper package including an upper package substrate, a system on chip (SoC) centrally mounted on an upper surface of the upper package substrate using an upper ball grid array (BGA), and the upper stiffener disposed along an outer edge of the upper package substrate;
- a lower package substrate that centrally mounts the upper package using a second BGA and includes the lower stiffener disposed on an upper surface of the lower package substrate to surround the upper package substrate;
- and
- a heat sink disposed on the upper package,
- wherein the upper stiffener is a square-ring having a rectangular cross-section,
- the lower stiffener includes a fence portion having a rectangular cross-section and a cover portion extending horizontally from an upper surface of the fence portion to contact an upper surface of the upper stiffener, and
- the upper stiffener and the lower stiffener are laterally spaced apart.
A semiconductor package comprising:
- a dual stiffener including an upper stiffener and a lower stiffener;
- an upper package including an upper package substrate, a semiconductor chip centrally mounted on an upper surface of the upper package substrate, and the upper stiffener disposed along an outer edge of the upper package substrate;
- a lower package substrate that centrally mounts the upper package and includes the lower stiffener disposed on an upper surface of the lower package substrate to surround the upper package substrate;
- and
- a heat sink disposed on the upper package and including a lower surface thermally contacting an upper surface of the semiconductor chip,
- wherein the upper stiffener has a square-ring shape and a rectangular cross-section, and
- the lower stiffener has a square-ring shape and includes a fence portion having a rectangular cross-section and a cover portion extending horizontally from an upper surface of the fence portion to contact an upper surface of the upper stiffener.
Dependencies are inferred from the claim text.