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US 11,908,750 B2Granted
Semiconductor device and method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShu Ling Liao, Chung-Chi Ko
Life of this patent
Estimating the term…
Abstract
An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, a first epitaxial source/drain region in the first fin and adjacent the first gate spacer, the first epitaxial source/drain region, and a protection layer between the first epitaxial source/drain region and the first gate spacer and between the first gate spacer and the first gate stack.
Claims20
A device comprising:
- a first fin extending from a substrate;
- a first gate stack over and along sidewalls of the first fin;
- a first gate spacer disposed along a sidewall of the first gate stack;
- a first epitaxial source/drain region in the first fin and adjacent the first gate spacer;
- a protection layer between the first epitaxial source/drain region and the first gate spacer, and the protection layer being between the first gate spacer and the first gate stack;
- and
- a first gate seal spacer underlying the protection layer, the first gate seal spacer being between the protection layer and the first gate stack.
4 more elements
A device comprising:
- a first fin extending from a substrate;
- a first gate stack over and along sidewalls of the first fin;
- a first gate seal spacer along a sidewall of the first gate stack;
- a first spacer footing over the first gate seal spacer;
- a protection layer disposed along a sidewall of the first gate seal spacer and a top surface of the first spacer footing;
- a first gate spacer disposed over the protection layer and the first spacer footing;
- and
- a first source/drain region in the first fin and adjacent the first gate spacer footing, the first spacer footing being between first gate seal spacer and the first source/drain region.
5 more elements
A device comprising:
- a first fin extending upwards from a substrate;
- a first gate over and along sidewalls of the first fin;
- a first source/drain region in the first fin adjacent the first gate;
- a protection layer over the first gate and the first source/drain region, the protection layer being between the first gate and the first source/drain region;
- a first gate spacer on the protection layer between the first gate and the first source/drain region, the first gate spacer comprising a low-k material;
- an etch stop layer over the first gate, the first gate spacer, and the first source/drain region;
- a first dielectric layer over the etch stop layer, the first dielectric layer having a top surface level with the first gate;
- a second dielectric layer over the first gate and the first dielectric layer;
- and
- a conductive contact through the first and second dielectric layers to the first source/drain region.
7 more elements
Dependencies are inferred from the claim text.