Method for designing three dimensional metal lines for enhanced device performance
AssigneeTokyo Electron Limited
InventorsMark I. Gardner, H. Jim Fulford
Life of this patent
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AssigneeTokyo Electron Limited
InventorsMark I. Gardner, H. Jim Fulford
Estimating the term…
A method of processing a substrate includes forming a first layer stack on a substrate, the first layer stack including conductive layers and dielectric layers that alternate in the first layer stack. An opening is formed in the first layer stack, the opening extending through each of the conductive layers in the first layer stack such that sidewalls of each of the conductive layers are exposed within the opening. A second stack of layers is formed within the opening, the second stack of layers including channel layers of semiconductor material positioned in the second stack such that each channel layer contacts exposed sidewalls of a respective conductive layer of the first layer stack. Transistor channels are from the channel layers of the second stack such that each transistor channel extends between exposed sidewalls of a respective conductive layer within the opening.
A method of processing a substrate, the method comprising:
A method of processing a substrate, the method comprising:
Dependencies are inferred from the claim text.