Semiconductor device with non-conformal gate dieletric layers

A semiconductor device, comprising:

• a first semiconductor layer over a base semiconductor structure;
• a second semiconductor layer over the first semiconductor layer;
• a third semiconductor layer over the second semiconductor layer;
• first, second, and third interfacial layers surrounding the first, the second, and the third semiconductor layers respectively;
• first, second, and third gate dielectric layers surrounding the first, the second, and the third interfacial layers, respectively;
• and
• a common gate electrode surrounding the first, the second, and the third gate dielectric layers, wherein each of the first, the second, and the third gate dielectric layers has asymmetric thicknesses below and above the respective first, second, and third interfacial layers.

A method, comprising:

• receiving a structure in a processing chamber, wherein the structure includes multiple semiconductor layers suspended over a semiconductor substrate;
• forming an interfacial layer surrounding each of the semiconductor layers;
• forming a gate dielectric layer over the interfacial layer and surrounding each of the semiconductor layers;
• and
• forming a gate electrode over the gate dielectric layer and surrounding each of the semiconductor layers,
• wherein the forming of the gate dielectric layer includes:
• introducing a first precursor into the processing chamber for a first duration,
• performing a first purging process for a second duration,
• introducing a second precursor into the processing chamber for a third duration,
• performing a second purging process for a fourth duration, and
• repeating the introducing the first precursor, performing the first purging process, introducing the second precursor, and performing the second purging process to form the gate dielectric layer having asymmetric thicknesses around each of the semiconductor layers.