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US 11,908,692 B2Granted
Method for fabricating a chip package
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJie Chen, Hsien-Wei Chen, Tzuan-Horng Liu, Ying-Ju Chen
Life of this patent
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Abstract
A first mask and a second mask are sequentially provided to perform a multi-step exposure and development processes. Through proper overlay design of the first mask and the second mask, conductive wirings having acceptable overlay offset are formed.
Claims20
A method, comprising:
- performing a first exposure process using a first mask to transfer a first layout pattern of the first mask onto a photoresist layer;
- performing a first development process to form a first wiring opening with the first layout pattern in the photoresist layer;
- after performing the first development process, performing a second exposure process using a second mask to transfer a second layout pattern of the second mask onto the photoresist layer, wherein the second layout pattern transferred onto the photoresist layer is substantially aligned with and overlaps an overlay region of the first wiring opening;
- performing a second development process to form a second wiring opening with the second layout pattern in the photoresist layer, wherein the first wiring opening and the second wiring opening are communicated at the overlay region;
- and
- after performing the second development process, forming a conductive wiring in the first wiring opening and the second wiring opening.
3 more elements
A method, comprising:
- performing a first exposure process using a first mask to transfer a first alignment pattern and a first layout pattern onto a photoresist layer;
- performing a first development process to form a first alignment opening and a first wiring opening in the photoresist layer;
- performing a second exposure process using a second mask to transfer a second alignment pattern and a second layout pattern onto the photoresist layer, wherein the second layout pattern transferred onto the photoresist layer is substantially aligned with and overlaps an overlay region of the first wiring opening, and the second alignment pattern of the second mask is substantially aligned with the first alignment opening formed in the photoresist layer when performing the second exposure process;
- performing a second development process to form a second alignment opening and a second wiring opening in the photoresist layer, wherein the first wiring opening and the second wiring opening are communicated at the overlay region;
- forming alignment marks in the first alignment opening and the second alignment opening;
- and
- forming a conductive wiring in the first wiring opening and the second wiring opening.
4 more elements
A method for fabricating a chip package, comprising:
- laterally encapsulating an integrated circuit component with an insulating encapsulation;
- forming a conductive layer over the integrated circuit component and the insulating encapsulation;
- patterning the photoresist layer, comprising:
- performing a first exposure process using a first mask to transfer a first alignment pattern and a first layout pattern onto a photoresist layer;
- performing a first development process to form a first alignment opening and a first wiring opening in the photoresist layer;
- performing a second exposure process using a second mask to transfer a second alignment pattern and a second layout pattern onto the photoresist layer, wherein the second layout pattern transferred onto the photoresist layer is substantially aligned with and overlaps an overlay region of the first wiring opening, and the second alignment pattern of the second mask is substantially aligned with the first alignment opening formed in the photoresist layer when performing the second exposure process;
- performing a second development process to form a second alignment opening and a second wiring opening in the photoresist layer, wherein the first wiring opening and the second wiring opening are communicated at the overlay region;
- forming alignment marks in the first alignment opening and the second alignment opening;
- and
- forming a conductive wiring in the first wiring opening and the second wiring opening, wherein the conductive wiring is electrically connected to the integrated circuit component.
7 more elements
Dependencies are inferred from the claim text.