Memory device and operating method for computing-in-memory

A memory device for computing in memory (CIM), comprising:

• a plurality of memory banks, each of the plurality of memory banks comprising:
• a first memory array, comprising least one bit line;
• a plurality of latch circuits, coupled to the least one bit line, configured to latch data on the least one bit line;
• and
• a local multiply accumulate (MAC) circuit, coupled to the plurality of latch circuits, configured to perform a first stage CIM operation on latched data latched in the plurality of latch circuits to provide a first stage CIM result;
• and
• a global MAC circuit, coupled to the plurality of memory banks, configured to perform a second stage CIM operation on a plurality of first stage CIM results from the plurality of memory banks.

An operating method for computing-in-memory (CIM) of a memory device, wherein the memory device comprises a plurality of memory banks and a global multiply accumulate (MAC) circuit, wherein each of the plurality of memory banks comprises first memory array, a first latch circuit, a second latch circuit and a local MAC circuit, wherein the operating method comprises:

• latching, using the first latch circuit, a first data from the first memory array in a first read cycle;
• latching, using the second latch circuit, a second data from the first memory array in a second read cycle in a second read cycle different from the first read cycle;
• performing, using the local MAC circuit, a first stage CIM operation on at least one of a first latched data latched in the first latch circuit and a second latched data latched in the second latch circuit to provide a first CIM result;
• and
• performing, using the global MAC circuit, a second stage CIM operation on a plurality of first stage CIM results from the plurality of memory banks.