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US 11,908,543 B2Granted
Latch circuit, transmission circuit including latch circuit, and semiconductor apparatus including transmission circuit
AssigneeSK hynix Inc.
InventorsEun Ji Choi, Keun Seon Ahn, Kwan Su Shon, Yo Han Jeong
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Abstract
The present technology may include a first detection unit configured to generate an output signal by detecting a level of an input terminal in response to a transition of a control clock signal during a normal read operation, and a second detection unit configured to generate the output signal by detecting the level of the input terminal regardless of the transition of the control clock signal during a state information read operation.
Claims20
A latch circuit comprising:
- a first detection unit configured to generate an output signal by detecting a level of an input terminal in response to a transition of a control clock signal during a normal read operation;
- and
- a second detection unit configured to generate the output signal by detecting the level of the input terminal in response to the control clock signal during a state information read operation,
- wherein the control clock signal transits repeatedly during the normal read operation, and the control clock signal is fixed to a first logic level during the state information read operation.
1 more element
A latch circuit comprising:
- a cross-coupled latch configured to latch a level of an input terminal in response to a transition of a control clock signal and output latched data through an output terminal;
- and
- a switching section, connected between the output terminal and the input terminal, configured to output state information, which is input through the input terminal, through the output terminal in response to a state information read signal regardless of a transition of the control clock signal.
A transmission circuit comprising:
- a latch circuit configured to:
- generate output signals by detecting levels of each data, which are input through a plurality of differential input terminals, according to each of a rising edge and a falling edge of control clock signals during a normal read operation, and
- generate the output signals by detecting a level of state information, which is input through the plurality of differential input terminals, in response to the control clock signals during a state information read operation;
- and
- a serializer configured to serialize and output the output signals,
- wherein the control clock signals transits repeatedly during the normal read operation, and the control clock signals are fixed to a first logic level during the state information read operation.
3 more elements
A semiconductor apparatus comprising:
- a memory cell array configured to store normal data;
- a control circuit configured to generate control signals including multi-phase clock signals in response to an external clock signal and configured to output internally stored state information in response to a state information read command;
- an input/output pad unit;
- and
- a transmission circuit configured to:
- generate output signals by detecting levels of each of the normal data, which are input through a plurality of differential input terminals, according to each of a rising edge and a falling edge of control clock signals and to output the output signals to an external device through the input/output pad unit during a normal read operation, and
- generate the output signals by detecting a level of state information, which is input through the plurality of differential input terminals, in response to the control clock signals and to output the output signals to an external device through the input/output pad unit during a state information read operation,
- wherein the control clock signals transits repeatedly during the normal read operation, and the control clock signals are fixed to a first logic level during the state information read operation.
5 more elements
Dependencies are inferred from the claim text.