Memory device detecting leakage current and operation method thereof

A memory device comprising:

• a first memory block connected to a first word line;
• a row decoder configured to control a voltage of the first word line through a first driving line;
• and
• a leakage detecting circuit configured to output a first detection signal by:
• detecting a first leakage current through the first driving line other than the first word line during a first time interval,
• storing a first voltage corresponding to the first leakage current during a second time interval,
• detecting a second leakage current through the first driving line during a third time interval, and
• detecting a third leakage current through the first word line based on the first voltage and the second leakage current.

An operation method of a memory device including a plurality of memory blocks and a leakage detecting circuit configured to detect a leakage current, the method comprising:

• precharging a first current path with a first voltage;
• floating the first current path from the first voltage to detect a first voltage variation corresponding to a first leakage current on the first current path;
• storing the first voltage variation in a first capacitor of the leakage detecting circuit;
• precharging the first current path and a second current path with the first voltage;
• floating the first current path and the second current path from the first voltage to detect a second voltage variation corresponding to a sum of the first leakage current on the first current path and a second leakage current on the second current path;
• and
• outputting, by the leakage detecting circuit, a first detection signal corresponding to the second leakage current based on the first voltage variation stored in the first capacitor and the second voltage variation,
• wherein the leakage current includes the first leakage current and the second leakage current.