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US 11,908,520 B2Granted
Memory device
AssigneeKioxia Corporation
InventorHideto Takekida
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a memory device includes a first chip and a second chip provided over the first chip. The first chip includes a first substrate, a first electrode, and a first memory cell array provided between the first substrate and the first electrode. The second chip includes a second substrate, a second electrode in contact with the first electrode, and a second memory cell array provided between the second substrate and the second electrode.
Claims17
A memory device comprising:
- a first chip;
- and
- a second chip bonded to the first chip,
- wherein the first chip includes a first substrate, a first circuit provided on the first substrate, a first electrode facing a bonding surface of the first chip and the second chip with the first electrode electrically connected to the first circuit, and a first memory cell array provided between the first substrate and the first electrode and electrically connected to the first circuit, and
- the second chip includes a second substrate, a second circuit provided on the second substrate, a second electrode facing the bonding surface with the second electrode electrically connected to the second circuit and being in contact with the first electrode, and a second memory cell array provided between the second substrate and the second electrode with the second memory cell array electrically connected to the second circuit.
2 more elements
A method, comprising:
- providing a first chip including a first substrate, a first circuit provided on the first substrate, a first electrode, and a first memory cell array;
- providing a second chip including a second substrate, a second circuit provided on the second substrate, a second electrode, and a second memory cell array;
- and
- bonding the first chip to the second chip through the first and second electrodes, such that the one or more first decoders are coupled to the first memory cell array, the first electrode faces a bonding surface of the first chip and the second chip with the first electrode electrically connected to the first circuit, the first memory cell array is provided between the first substrate and the first electrode and electrically connected to the first circuit, the second electrode faces the bonding surface with the second electrode electrically connected to the second circuit and being in contact with the first electrode, and the second memory cell array is provided between the second substrate and the second electrode and electrically connected to the second circuit.
1 more element
Dependencies are inferred from the claim text.