Memory device and method for operating the same
AssigneeNanya Technology Corporation
InventorKuo-Chiang Hung
Life of this patent
Estimating the term…
Abstract
A memory device includes a first chip, a second chip and a processor. The second chip is coupled to the first chip at a first node. The second chip includes a first capacitor and a first variable resistor. The first capacitor is coupled to the first node. The first variable resistor is coupled in series with the first capacitor. The processor is coupled to the first node, and is configured to perform a first read operation to the first chip via the first node. A method for operating a memory device is also disclosed herein.
Claims20
A memory device, comprising:
- a first chip;
- a second chip coupled to the first chip at a first node, and comprising:
- a first capacitor coupled to the first node;
- and
- a first variable resistor coupled in series with the first capacitor;
- and
- a processor coupled to the first node, and configured to perform a first read operation to the first chip via the first node.
A method for operating a memory device, comprising:
- adjusting a resistance of a first chip to a first resistance, wherein the first chip is coupled to a first node;
- after the resistance of the first chip is adjusted to the first resistance, writing first data stored in a second chip into a processor via the first node;
- adjusting the resistance of the first chip to a second resistance lower than the first resistance;
- and
- after the resistance of the first chip is adjusted to the second resistance, writing second data stored in the first chip into the processor via the first node.
A memory device, comprising:
- a first chip configured to store first data;
- a second chip coupled to the first chip at a first node;
- and
- a processor configured to read the first data via the first node, and configured to increase a resistance of the second chip in response to reading the first data via the first node.
Dependencies are inferred from the claim text.