Ferroelectric FET-based content addressable memory

A data processing device, comprising:

• a plurality of wordlines (“WLs”);
• a plurality of matchline-enable (“ML-enable”) lines;
• a plurality of bitlines (“BLs”);
• a plurality of selectlines (“SLs”);
• a plurality of inputlines (“INs”);
• a plurality of data storage units arranged logically in a plurality of rows and a plurality of columns, each of the rows of data storage units associated with a respective one of the WLs and respective one of the ML-enable lines, each of the columns of the data storage units being connected to a respective one of the BLs, a respective one of the SLs and a respective one of the INs, each of the data storage units comprising:
• a matchline (“ML”) switching transistor having a gate, drain and source;
• a ferroelectric field-effect transistor (“FeFET”) having a gate, drain and source;
• and
• an input switching transistor having a gate, drain and source and being, with the drain connected to the source of the FeFET at a junction to form a serial combination between the input switching transistor and the FeFET, the gate of the FeFET being connected to the associated WL;
• a first end of the serial combination being connected to the associated BL;
• the junction between the input switching transistor and FeFET being connected to the associated SL;
• the gate of the input switch transistor being connected to the associated IN;
• the ML switching transistors in each row of the data storage devices are connected to each other source-to-drain at the plurality of BLs, forming a matchline having an input end and an output end, the gates of the ML switching transistors in each row of the data storage devices are connected to the associated ML-enable line.

A data processing method, comprising:

• storing in a memory array a first sequence of a first plurality of binary patterns, each of which representing a binary “0”, “1” or “X” (don't-care);
• providing a second sequence of a second plurality of binary pattern, each corresponding to a respective one of the first plurality of binary patterns and being indicative of a binary “0”, “1” or “X”;
• comparing each of the first plurality of binary patters with the corresponding one of the second plurality of binary patterns;
• and
• generating a signal indicative of a match between the first and second sequences if each binary pattern in the first sequence and the corresponding binary pattern in the second sequence are identical to each other, or at least one of the two binary patterns is indicative of an “X,”
• wherein storing a first plurality of binary patterns comprises storing a first plurality of binary value pairs in respective pairs of first and second data storage units in a memory cell, each of data storage units including:
• a matchline (“ML”) switching transistor;
• and
• a ferroelectric field-effect transistor (“FeFET”) and an input switching transistor, each of the ML switching transistor, FeFET and input switching transistor having a gate, a source and a drain, and the FeFET having a threshold voltage for altering its memory state, the drain of the input switching transistor being connected to the source of the FeFET,
• the source of the ML switching transistor of the first data storage unit being connected to drain of the ML switching transistor of the second data storage unit at a junction, forming a serial combination having a first end and a second end,
• the drain of the FeFET in the first data storage unit being connected to the first end of the serial combination of the ML switching transistors at a junction, and the drain of the FeFET in the second data storage units being connected to the junction between the ML switching transistors.