Front end buffer having ferroelectric field effect transistor (FeFET) based memory

An apparatus comprising:

• a buffer memory formed of ferroelectric field effect transistors (FeFETs);
• a program driver configured to write data to the FeFETs to store an existing pattern to the FeFETs;
• a read driver configured to read data from the FeFETs to read the existing pattern from the FeFETs;
• a refresh circuit configured to selectively rewrite the existing data pattern back to the FeFETs after a read operation carried out by the read driver;
• a sense circuit configured to sense the existing pattern stored to the FeFETs;
• a monitor circuit configured to monitor operation of the FeFETs;
• an optimization controller configured to adjust at least one operational parameter associated with the FeFETs responsive to the monitored operation by the monitor circuit;
• a non-volatile memory (NVM) arranged as a main store for user data, wherein the NVM comprises control lines having a first width, and wherein the FeFETs in the buffer memory have a control lines with a second width, the second width being larger than the first width;
• and
• wherein the monitored operation by the monitor circuit comprises at least a selected one of a bit error rate (BER) associated with the transfers of data to and from the buffer, data aging of an existing data pattern stored to the FeFETs or a write count associated with total accumulated number of data programming operations upon the FeFETs by the program driver.