Nonvolatile memory devices having enhanced write drivers therein

A nonvolatile memory device, comprising:

• an array of magnetic memory cells;
• a control logic circuit having a voltage generator therein, which is configured to generate a gate voltage, said control logic circuit configured to determine data stored in the magnetic memory cells upon commencement of a write operation and thereafter perform the write operation when the data stored in the magnetic memory cells is different from the data to be written to the magnetic memory cell during the write operation;
• a row decoder comprising a word line driver, which is driven by the gate voltage and connected to the array of magnetic memory cells by word lines;
• a column decoder connected to the array of magnetic memory cells by bit lines and source lines;
• and
• a write driver having a write voltage generating circuit therein, said write driver configured to transmit a write voltage to a bit line selected by the column decoder when performing a write operation;
• and
• wherein the write voltage generating circuit is configured to generate the write voltage based on:
• (i) a reference voltage generated using a replica magnetic memory cell, and (ii) a feedback voltage generated using a magnetic memory cell in which the write operation is to be performed.

A nonvolatile memory device, comprising:

• an array of magnetic memory cells having a plurality of memory cell groups therein;
• a control logic circuit comprising a voltage generator, which is configured to generate a gate voltage;
• a row decoder having a word line driver therein, which is driven by the gate voltage and connected to the memory cell array through word lines;
• a column decoder connected to the memory cell array through bit lines and source lines;
• and
• a write driver having a write voltage generating circuit therein, which is configured to output:
• (i) a write voltage proportional to a reference voltage generated using a replica magnetic memory cell based on the reference voltage, and (ii) a compensation voltage generated using a compensation circuit operating as a source follower including a PMOS transistor, and transmit the write voltage to a bit line selected by the column decoder when performing a write operation.