Display panel and pixel driving method

A pixel driving method for driving a display panel, the pixel driving method comprising:

• an initialization stage, a sampling compensation stage, and a displaying light emitting stage;
• wherein the initialization stage comprises:
• providing a low level signal to an anode of a light emitting device through a second power line, while providing a first level signal to a second response terminal through a first control line, providing a second level signal to a third response terminal through a second control line, providing a third level signal to a third connection terminal through a first power line, and providing a fourth level signal to a data writing terminal through a data line, so as to have the third connection terminal and the fourth connection terminal turned on, the data writing terminal and the fifth connection terminal turned on, and the sixth connection terminal and the seventh connection terminal turned on;
• wherein the sampling compensation stage comprises:
• providing a low level signal to the anode of the light emitting device through the second power line, while providing a fifth level signal to the second response terminal through the first control line, providing a sixth level signal to the third response terminal through the second control line, providing a seventh level signal to the third connection terminal through the first power line, and providing an eighth level signal to the data writing terminal through the data line, so as to have the third connection terminal and the fourth connection terminal turned off, the data writing terminal and the fifth connection terminal turned on, and the sixth connection terminal and the seventh connection terminal turned on;
• and
• wherein the displaying light emitting stage comprises:
• providing a high level signal to the anode of the light emitting device through the second power line, while providing a ninth level signal to the second response terminal through the first control line, providing a tenth level signal to the third response terminal through the second control line, providing an eleventh level signal to the third connection terminal through the first power line, and providing a twelfth level signal to the data writing terminal through the data line, so as to have the third connection terminal and the fourth connection terminal turned off, the data writing terminal and the fifth connection terminal turned off, and the sixth connection terminal and the seventh connection terminal turned off;
• wherein the display panel comprises:
• a plurality of pixel driving circuits arranged in an array along a row direction and a column direction;
• wherein the display panel further comprises a plurality of first control lines, a plurality of second control lines, a plurality of data lines, and a plurality of power lines;
• wherein each of the pixel driving circuits is correspondingly connected to the first control line, the second control line, the data line, and two power lines, and the two power lines comprises the first power line and the second power line;
• wherein the pixel driving circuit comprises:
• a driving transistor having a control terminal connected to a point G, a first terminal connected to a point D, and a second terminal connected to ground;
• a storage capacitor having a first terminal connected to the point G, and a second terminal connected to ground;
• a sampling compensation assembly, comprising a first response terminal connected to the point G, a first connection terminal connected to a point A, and a second connection terminal connected to a point B, the first response terminal being configured to respond to a level signal at the point G to control an on-off state between the first connection terminal and the second connection terminal;
• a first switch assembly, comprising the second response terminal connected to the first control line, the third connection terminal connected to the first power line of the two power lines, and the fourth connection terminal connected to the point B, the second response terminal being configured to respond to a level signal provided by the first control line to control an on-off state between the third connection terminal and the fourth connection terminal;
• and
• a second switch assembly, comprising the third response terminal connected to the second control line, the data writing terminal connected to the data line, the fifth connection terminal connected to the point A, the sixth connection terminal connected to the point B, and the seventh connection terminal connected to the point G, the third response terminal being configured to respond to a level signal provided by the second control line to control an on-off state between the data writing terminal and the fifth connection terminal and an on-off state between the sixth connection terminal and the seventh connection terminal;
• wherein the light emitting device has a cathode connected to the point D and the anode is connected to the second power line of the two power lines, the second power line being configured to provide a high level signal during the displaying light emitting stage and a low level signal in other stages;
• wherein the power lines extend in a row direction, and the power lines and the pixel driving circuit each comprises N rows;
• wherein in a first row of the pixel driving circuit, the anode of the light emitting device is connected to a first row of the power line, and the third connection terminal of the first switch assembly is connected to an N-th row of the power line, wherein the first row of the power line is the second power line of the two power lines, and the N-th row of the power line is the first power line of the two power lines;
• wherein in an n-th first row of the pixel driving circuit, the anode of the light emitting device is connected to the n-th row of the power line, and the third connection terminal of the first switch assembly is connected to an n-1-th row of the power line;
• wherein the n-th row of the power line is the second power line of the two power lines, and the n-1-th row of the power line is the first power line of the two power lines;
• wherein n and N are positive integers, and 1<n≤N;
• wherein in the sampling compensation stage, the light emitting device is in a reversed-biased state;
• wherein in the displaying light emitting stage, the light emitting device switches to a forward-biased state.