Gate driving circuit and display panel

A gate driving circuit, comprising a plurality of cascaded gate driving units, wherein each of the gate driving units comprises:

• a pull-up control transistor, wherein one of a source/drain of the pull-up control transistor is connected to a Jth stage scanning line, a gate of the pull-up control transistor is connected to a Jth stage cascade line, and another one of the source/drain of the pull-up control transistor is connected to the pull-up node;
• a first transistor, wherein one of a source/drain of the first transistor is connected to a first low frequency control line and a gate of the first transistor;
• a second transistor, wherein one of a source/drain of the second transistor is connected to the one of the source/drain of the first transistor, and a gate of the second transistor is connected to another one of the source/drain of the first transistor;
• a third transistor, wherein one of a source/drain of the third transistor is connected to another one of the source/drain of the first transistor, a gate of the third transistor is connected to the pull-up node, and another one of the source/drain of the third transistor is connected to the first low potential line;
• a fourth transistor, wherein one of a source/drain of the fourth transistor is connected to another one of the source/drain of the second transistor, a gate of the fourth transistor is connected to the pull-up node, and another one of the source/drain of the fourth transistor is connected to the first low potential line;
• a first feedback transistor, wherein one of a source/drain of the first feedback transistor is connected to the pull-up node, a gate of the first feedback transistor is connected to both another one of the source/drain of the second transistor and the one of the source/drain of the fourth transistor, and another one of the source/drain of the first feedback transistor is connected to the first low potential line;
• wherein the Jth stage scanning line is configured to transmit a Jth stage scanning signal having a trimmed rising edge, and the Jth stage cascade line is configured to transmit a Jth stage cascade signal having a trimmed rising edge;
• wherein each of the gate driving units further includes:
• a fifth transistor, wherein one of a source/drain of the fifth transistor is connected to both a second low frequency control line and a gate of the fifth transistor;
• a sixth transistor, wherein, one of a source/drain of the sixth transistor is connected to the one of the source/drain of the fifth transistor, and a gate of the second transistor is connected to another one of the source/drain of the fifth transistor;
• a seventh transistor, wherein, one of a source/drain of the seventh transistor is connected to another one of the source/drain of the fifth transistor, a gate of the seventh transistor is connected to the pull-up node, and another one of the source/drain of the seventh transistor is connected to the first low potential line;
• an eighth transistor, wherein, one of a source/drain of the eighth transistor is connected to another one of the source/drain of the sixth transistor, a gate of the eighth transistor is connected to the pull-up node, and another one of the source/drain of the eighth transistor is connected to the first low potential line;
• and a second feedback transistor, wherein, one of a source/drain of the second feedback transistor is connected to the pull-up node, a gate of the second feedback transistor is connected to both another one of the source/drain of the sixth transistor and the one of the source/drain of the seventh transistor, and another one of the source/drain of the second feedback transistor is connected to the first low potential line;
• wherein each of the gate driving units further includes:
• a pull-up transistor, wherein one of a source/drain of the pull-up transistor is connected to an Nth stage clock line, a gate of the pull-up transistor is connected to the pull-up node, and another one of the source/drain of the pull-up transistor is connected to an Nth stage scanning line;
• and a cascade transistor, wherein one of a source/drain of the cascade transistor is connected to the Nth stage clock line, a gate of the cascade transistor is connected to the pull-up node, and another one of the source/drain of the cascade transistor is connected to an Nth stage cascade line;
• wherein the Nth stage clock line is configured to transmit an Nth stage clock signal having a trimmed rising edge;
• the Nth stage scanning line is configured to transmit an Nth stage scanning signal having a trimmed rising edge, a waveform of the Nth stage scanning signal is the same as a waveform of the Jth stage scanning signal and a phase of the Nth stage scanning signal lags behind a phase of the Jth stage scanning signal;
• a waveform of the Nth stage cascade signal is the same as a waveform of the Jth stage cascade signal, and a phase of the Nth stage cascade signal lags behind a phase of the Jth stage cascade signal;
• and
• wherein, an initial moment of the trimmed rising edge is the same as an initial moment of a rising edge of the Nth stage clock signal in timing, and a ratio of a duration of the trimmed rising edge to a pulse duration of the Nth stage clock signal is greater than or equal to ¼ and less than or equal to ⅓.