Inter-warp sharing of general purpose register data in GPU

A method for operating a graphics processing unit (GPU), the GPU comprising a processing cluster, the processing cluster comprising a plurality of processing cores configured to execute a warp of related threads, each processing core of the plurality of processing cores executing a separate thread of the warp of related threads in parallel, the GPU further comprising a shared memory for the processing cluster, the method comprising:

• receiving, by a processing core of the plurality of processing cores, a move data instruction of an instruction set architecture of the GPU, the move data instruction comprising operands that reference a source portion of a general purpose register (GPR) and a destination portion of the GPR, each processing core of the plurality of processing cores configured to utilize a respective dedicated portion of the GPR when processing instructions, wherein the processing core is configured to utilize the source portion of the GPR referenced by the move data instruction;
• executing, by the processing core, the move data instruction to:
• retrieve data from the source portion of the GPR;
• and
• provide the retrieved data to a memory read/write hub, the memory read/write hub coupled to the GPR and the shared memory, the memory read/write hub comprising a crossbar switch;
• and
• writing, by the memory read/write hub via the crossbar switch, the retrieved data to the destination portion of the GPR, the writing of the retrieved data occurring without first writing the retrieved data to the shared memory.

A multiprocessor apparatus comprising:

• a plurality of processing clusters, each of the plurality of processing clusters configured to execute a grouping of related threads in parallel, each of the plurality of processing clusters comprising:
• a general purpose register (GPR);
• a plurality of processing cores, each processing core of the plurality of processing cores comprising a temporary register, wherein each processing core of the plurality of processing cores is configured to utilize a respective dedicated portion of the GPR when processing instructions;
• a shared memory for the plurality of processing cores;
• and
• a memory read/write hub coupled to the GPR and the shared memory, the memory read/write hub comprising a crossbar switch,
• wherein the multiprocessor apparatus is configured to execute instructions of an instruction set architecture, the instructions of the instruction set architecture comprising a move data instruction comprising operands that reference a source temporary register and a destination portion of the GPR;
• and
• in response to execution of the move data instruction:
• a processing core of the plurality of processing cores is configure to retrieve data from the source temporary register;
• and
• the memory read/write hub is configured to write, via the crossbar switch, the retrieved data to the destination portion of the GPR, the writing of the retrieved data occurring without first writing the retrieved data to the shared memory.