Deep neural network on field-programmable gate array

A method for inference of a trained deep neural network (DNN) using a field programmable gate array (FPGA), the trained DNN comprising a set of parameters, wherein the FPGA has a first precision configuration defining first number representations of the set of parameters, the method comprising:

• mapping the trained DNN to the FPGA via a configuration map, the mapping comprising:
• partitioning the FPGA into a static region and a reconfigurable dynamic region;
• partitioning the reconfigurable dynamic region into sub-regions;
• and
• mapping the trained DNN to the sub-regions of the reconfigurable dynamic region;
• determining different precision configurations of the trained DNN, wherein a precision configuration of the different precision configurations defines second number representations of a subset of the set of parameters;
• compiling a combination of layers of the trained DNN for each of the different precision configurations;
• providing, for each of the different precision configurations, a bitstream file for enabling programming of the FPGA, in accordance with the precision configuration;
• precompiling a bitstream pool with the bitstream files;
• storing the bitstream files;
• and
• programming the FPGA using one of the stored bitstream files for inference of the DNN and the configuration map, wherein the programming of the FPGA is performed automatically.