Communication in a computer having multiple processors
AssigneeGraphcore Limited
InventorsRichard Osborne, Matthew Fyles
Life of this patent
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Abstract
A computer comprising a plurality of processors, each of which are configured to perform operations on data during a compute phase for the computer and, following a pre-compiled synchronisation barrier, exchange data with at least one other of the processors during an exchange phase for the computer, wherein of the processors in the computer is indexed and the data exchange operations carried out by each processor in the exchange phase depend upon its index value.
Claims19
A system comprising:
- a plurality of chips, the plurality of chips including a first chip and a second chip, wherein the first chip includes:
- at least one storage comprising a program having a set of executable instructions and an index value identifying the first chip among the plurality of chips;
- at least one data memory configured to store data for use in calculations specified by the set of executable instructions;
- and
- at least one execution unit configured to execute the set of executable instructions,
- wherein the at least one execution unit is configured to execute the set of executable instructions to:
- generate a data packet having first data from the at least one data memory, including selecting the second chip as a destination to which the data packet is to be sent in dependence upon the index value identifying the first chip, and providing an address of the second chip in the data packet;
- and
- dispatch the data packet via routing hardware configured to route the data packet to the second chip.
A computer implemented method of generating multiple programs, each of which is suitable for execution by a processor of one of a plurality of chips, the method comprising:
- compiling a single set of executable instructions;
- determining a first index value for a first one of the chips and a second index value for a second one of the chips;
- and
- generating, for the first one of the chips, a first local program comprising the single set of executable instructions and the first index value, and generating, for the second one of the chips, a second local program comprising the single set of executable instructions and the second index value,
- wherein the single set of executable instructions, when allocated to the first one of the chips is scheduled to execute on a first processor of the first one of the chips to cause:
- in dependence upon the first index value, selecting a further one of the chips as a destination and providing an address of the further one of the chips in a data packet;
- and
- dispatching the data packet via routing hardware to the further one of the chips.
A non-transitory computer readable medium storing a computer program comprising multiple local programs each of which is suitable for execution by a processor of one of a plurality of chips, each of the local programs comprising:
- a set of executable instructions;
- and
- an index value, associated with one of the chips on which the local program is scheduled to run,
- wherein a first of the local programs, when allocated to a first one of the chips is scheduled to execute on a first processor of the first one of the chips to cause:
- in dependence upon a first of the index values that is associated with the first one of the chips, selecting a further one of the chips as a destination and providing an address of the selected further one of the chips in a data packet;
- and
- dispatching the data packet via first routing hardware to the further one of the chips.
Dependencies are inferred from the claim text.