Integrated circuit layout generation method

A method of generating an integrated circuit (IC) layout diagram, the method comprising:

• receiving a first gate resistance value of a gate region in an IC layout diagram, the first gate resistance value corresponding to a location of a gate via positioned within an active region and along a width of the gate region extending across the active region;
• determining a second gate resistance value based on the location and the width;
• altering a netlist by adding a second gate terminal node to a first gate terminal node corresponding to the gate region, and adding a resistor between the first and second gate terminal nodes, the resistor having a resistance value equal to the first gate resistance value subtracted from the second gate resistance value;
• performing an alternating current (AC) simulation of an IC device corresponding to the IC layout diagram in which the AC simulation uses the resistor;
• based on the AC simulation, determining that the IC layout diagram does not comply with a design specification;
• and
• based on the non-compliance with the design specification, modifying the IC layout diagram.

A method of generating an integrated circuit (IC) layout diagram, the method comprising:

• receiving a first gate resistance value of a gate region in an IC layout diagram, the first gate resistance value corresponding to a location of a gate via positioned within an active region and along a width of the gate region extending across the active region;
• determining a second gate resistance value based on the location and the width;
• using the first and second resistance values by performing an alternating current (AC) simulation based on the IC layout diagram to determine that the IC layout diagram does not comply with a design specification;
• and
• based on the non-compliance with the design specification, modifying the IC layout diagram,
• wherein
• the active region corresponds to a fin field-effect transistor (FinFET), and
• the determining the second gate resistance value is based on a number of fins of the FinFET.