Reset domain crossing detection and simulation

A non-transitory computer readable storage medium including instructions that when executed by a processor enable the processor to:

• identify, in a circuit design, a first sequential element that belongs to a first reset domain and that generates a first output;
• identify, in the circuit design, a second sequential element that belongs to a second reset domain and that receives the first output as an input and generates a second output;
• and
• in response to determining metastability effects from metastability in the second output are unobservable at an observation point downstream from the second sequential element in the circuit design, simulating the circuit design with jitter injected on the first reset domain and not on the second reset domain.

A system comprising:

• a memory storing instructions;
• and
• a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:
• receive an integrated circuit (IC) design file;
• identify a reset domain crossing (RDC) path of the IC design file;
• inject, during a simulation of IC design file, a RDC jitter error signal into the RDC path;
• and
• generate a coverage report comprising one or more of reset assertion data, destination data toggle data, or jitter error data associated with the RDC jitter error signal in the RDC path.