US 11,907,580 B2 · Corrective read of a memory device with reduced latency

Abstract

Methods, systems, and devices for a corrective read of a memory device with reduced latency are described. A memory system may identify a read error based on accessing a memory device, and may select a trim setting for a performing a corrective read operation based on a data retention condition associated with the accessed memory device. Such a data retention condition may be associated with a data retention duration, or a cross-temperature condition, among other criteria or combinations thereof. In some implementations, the memory system may select from a subset of possible trim settings, which may be associated with relevant process corners. For example, the memory system may select between a first trim setting that is associated with a relatively large cross-temperature and a relatively short data retention duration and a second trim setting that is associated with a relatively small cross-temperature and a relatively long data retention duration.

Claims21

Dependent claims

An apparatus, comprising:

a memory device;
and
a controller coupled with the memory device and configured to cause the apparatus to:
identify a read error based at least in part on receiving, from the memory device, first information that is associated with a first read operation of the memory device;
select a trim setting from a plurality of trim settings based at least in part on identifying a data retention condition associated with the first information;
transmit, to the memory device, an indication to initiate a second read operation of the memory device in accordance with the selected trim setting;
and
perform a decoding operation based at least in part on receiving, from the memory device, second information that is associated with the second read operation of the memory device.

5 more elements

A non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of an electronic device, cause the electronic device to:

identify a read error based at least in part on receiving, from a memory device, first information that is associated with a first read operation of the memory device;
select a trim setting from a plurality of trim settings based at least in part on identifying a data retention condition associated with the first information;
transmit, to the memory device, an indication to initiate a second read operation of the memory device in accordance with the selected trim setting;
and
perform a decoding operation based at least in part on receiving, from the memory device, second information that is associated with the second read operation of the memory device.

2 more elements

Dependencies are inferred from the claim text.

Corrective read of a memory device with reduced latency

Life of this patent

Corrective read of a memory device with reduced latency

Life of this patent

Abstract

Claims21