High performance, high capacity memory modules and systems

A memory module comprising:

• a printed-circuit (PC) board having a first side, a second side, and a module connector with module data connections and module control connections;
• an address-buffer component coupled to the module control connections via a module control interface;
• a first memory die on the first side of the PC board and coupled to the address-buffer component via a first memory-die control interface;
• a second memory die on the second side of the PC board and coupled to the address-buffer component via a second memory-die control interface;
• and
• a first data-buffer component on the first side of the PC board and coupled between a first subset of the module data connections and the first memory die;
• and
• a second data-buffer component on the second side of the PC board and coupled between a second subset of the module data connections and the second memory die;
• the first and second data-buffer components supporting:
• a first-width-data mode to steer first-width data on the first subset of module data connections to the first memory die and the second memory die;
• and
• a second-width-data mode to steer second-width data on the first and second subsets of module data connections to only one of the first memory die and the second memory die;
• the address-buffer component simultaneously asserting a first chip-select signal on the first memory-die control interface and a second chip-select signal the second memory-die control interface in the first-width-data mode and asserting only one of the first chip-select signal and the second chip-select signal in the second-width-data mode.

A memory comprising:

• a printed-circuit (PC) board having a first side, a second side, and a connector with data connections and control connections;
• an address-buffer component on the first side of the PC board and coupled to the control connections;
• a first memory die on the first side of the PC board and coupled to the address-buffer component via a first memory-die control interface;
• a second memory die on the second side of the PC board and coupled to the address-buffer component via a second memory-die control interface;
• and
• a first data-buffer component on the first side of the PC board and coupled between a first subset of the data connections and the first memory die;
• and
• a second data-buffer component on the second side of the PC board and coupled between a second subset of the data connections and the second memory die;
• the first and second data-buffer components supporting:
• a first-width-data mode to steer first-width data on a first subset of the data connections to the first memory die and the second memory die;
• and
• a second-width-data mode to steer second-width data on the first subset of the data connections and a second subset of the data connections to only one of the first memory die and the second memory die;
• the address-buffer component simultaneously asserting a first chip-select signal on the first memory-die control interface and a second chip-select signal the second memory-die control interface in the first-width-data mode and asserting only one of the first chip-select signal and the second chip-select signal in the second-width-data mode.